Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

A.4.4.2.2. CSEL Settings for the NAND Controller

Table 276.  NAND Controller CSEL Pin Settings
Setting CSEL[1:0] Pin Value
0 1 2 3

osc1_clk (HPS1_CLK pin) range

10–50 MHz

10–12.5 MHz

12.5–25 MHz

25–50 MHz

Device frequency (nand_x_clk/4)

osc1_clk/4, 12.5 MHz max

osc1_clk*8/4, 25 MHz max

osc1_clk*4/4, 25 MHz max

osc1_clk2/4, 25 MHz max

Controller clock (nand_x_clk)

osc1_clk, 50 MHz max

osc1_clk*8, 100 MHz max

osc1_clk*4, 100 MHz max

osc1_clk*2, 100 MHz max

mpu_clk

osc1_clk, 50 MHz max

osc1_clk*32, 400 MHz max

osc1_clk*16, 400 MHz max

osc1_clk*8, 400 MHz max

PLL modes

Bypassed

Locked

Locked

Locked