Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

18.6.2. EMAC FPGA Interface Initialization

To initialize the Ethernet controller to use the FPGA GMII/MII interface, specific software steps must be followed.

In general, the FPGA interface must be active in user mode with valid PHY clocks, the Ethernet Controller must be in a reset state during static configuration and the clock must be active and valid before the Ethernet Controller is brought out of reset.

  1. After the HPS is released from cold or warm reset, reset the Ethernet Controller module by setting the appropriate emac bit in the permodrst register in the Reset Manager.
  2. Configure the EMAC Controller clock to 250 MHz by programming the appropriate cnt value in the emac*clk register in the Clock Manager.
  3. Bring the Ethernet PHY out of reset to allow PHY to generate RX clocks and TX clocks.

    When using FPGA GMII/MII interface, you must have a stable RX clock (emac_clk_rx_i) and TX clock (emac_clk_tx_i) supply from PHY to EMAC before bringing EMAC out of reset.

    There are no registers to verify, but you can create the following custom logic block to cross check:
    • You can use Signal Tap to check, or create a simple counter block with the RX clock and TX clock as clock source to check if it runs.
  4. If the PTP clock source is from the FPGA, ensure that the FPGA f2s_ptp_ref_clk is active.
  5. The soft GMII/MII adaptor must be loaded with active clocks propagating. The FPGA must be configured to user mode and a reset to the user soft FPGA IP may be required to propagate the PHY clocks to the HPS.
  6. Once all clock sources are valid, apply the following clock settings:
    1. Program the physel_* field in the ctrl register of the System Manager (EMAC Group) to 0x0 to select the GMII/MII PHY interface.
    2. If the PTP clock source is from the FPGA, set the ptpclksel_* bit in the ctrl register (EMAC group) of the System Manager to be 0x1.
    3. Enable the Ethernet Controller FPGA interface by setting the emac_* bit in the module register of the System Manager (FPGA Interface group).
  7. Configure all of the EMAC static settings if the user requires a different setting from the default value. These settings include AXI AxCache signal values which are programmed in l3 register in the EMAC group of the System Manager.
  8. Execute a register read back to confirm the clock and static configuration settings are valid.
  9. After confirming the settings are valid, software can clear the emac bit in the permodrst register of the Reset Manager to bring the EMAC out of reset.
When these steps are completed, general Ethernet controller and DMA software initialization and configuration can continue.
Note: These same steps can be applied to convert the HPS GMII to an RGMII, RMII or SGMII interface through the FPGA, except that in step 5 during FPGA configuration, you would load the appropriate soft adaptor for the interface and apply reset to it as well. The PHY interface select encoding would remain as 0x0. For the SGMII interface additional external transceiver logic would be required. Routing the Ethernet signals through the FPGA is useful for designs that are pin-limited in the HPS.