Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

4. Reset Manager

The reset manager generates module reset signals based on reset requests from the various sources in the HPS and FPGA fabric, and software writing to the module-reset control registers. The reset manager ensures that a reset request from the FPGA fabric can occur only after the FPGA portion of the system-on-a-chip (SoC) device is configured.

The HPS contains multiple reset domains. Each reset domain can be reset independently. A reset may be initiated externally, internally or through software.

Table 17.  HPS Reset Domains

Domain Name

Domain Logic

TAP

JTAG test access port (TAP) controller, which is used by the debug access port (DAP).

Debug

All debug logic including most of the DAP, CoreSight* ™ components connected to the debug peripheral bus, trace, the microprocessor unit (MPU) subsystem, and the FPGA fabric.

System

All HPS logic except what is in the TAP and debug reset domains. Includes non-debug logic in the FPGA fabric connected to the HPS reset signals.

The HPS supports the following reset types:

  • System cold reset
    • Used to ensure the HPS is placed in a default state sufficient for software to boot
    • Triggered by a power-on reset and other sources
    • Resets all HPS logic that can be reset
    • Affects all reset domains
  • System warm reset
    • Occurs after HPS has already completed a cold reset
    • Used to recover system from a non-responsive condition
    • Resets a subset of the HPS state reset by a cold reset
    • Only affects the system reset domain, which allows debugging (including trace) to operate through the warm reset
  • Debug reset
    • Used to recover debug logic from a non-responsive condition
    • Only affects the debug reset domain