AN 447: Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

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ID 683295
Date 3/28/2022
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Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems x
Receiver Level Requirements Guideline: Use Internal PCI Clamp Diode on the Pin Guideline: Use Series Termination Resistor Guideline: Select Appropriate Driver Interface Current between Supported Intel® Devices Document Revision History for AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Guideline: Use Internal PCI Clamp Diode on the Pin x
Measuring DC Current with PCI Clamp Diode
Guideline: Use Series Termination Resistor x
Selecting Appropriate Series Termination Resistor Value Example of Determining Series Termination Resistor Value
Guideline: Select Appropriate Driver x
Driver Selection Reference Current Limits Measurement Examples Evaluating Interface Using Driver Selection Method
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

Guideline: Use Internal PCI Clamp Diode on the Pin

The supported Intel® devices provide an optional PCI clamp diode for each I/O pin. You can use this diode to protect I/O pins against voltage overshoot.

By default, if the assigned input, bidirectional, or tristated output pins use 3.3 V, 3.0 V, or 2.5 V LVTTL or LVCMOS I/O standards, the Intel® Quartus® Prime software enables the PCI clamp diode on the pin.

The PCI clamp diode can sufficiently clamp voltage overshoot to within the DC and AC input voltage specifications when the bank supply voltage (VCCIO) is 2.5 V or 3.0 V. You can clamp the voltage for a 3.3 V VCCIO to a level that exceeds the DC and AC input voltage specifications with ± 5% supply voltage tolerance. The clamped voltage is expressed as the sum of the supply voltage (VCCIO) and the diode forward voltage.

Note: Dual-purpose configuration pins support the diode in user mode if the specific pins are not used as configuration pins for the selected configuration scheme. Dedicated configuration pins do not support the on-chip diode.
Figure 2. PCI Clamp Diode in Supported Intel® Devices


The PCI clamp diode in the supported Intel® devices can support a maximum of 10 mA DC current. The diode sinks the DC current when driven by a voltage level that exceeds the bank VCCIO plus the diode forward voltage. You must take the DC sink current into consideration when you interface a 2.5 V VCCIO receiver on the supported Intel® device with 3.0 V and 3.3 V LVTTL or LVCMOS I/O systems.

Note: The 10 mA DC current limit refers to the current that the diode sinks and not the drive strength of the driver. This limit is only applicable when the PCI clamp diode is enabled and when the 2.5 V receiver of the supported Intel® device interfaces with 3.0 V or 3.3 V LVTTL or LVCMOS I/O systems.

If you disable the diode in the Intel® Quartus® Prime software, ensure that the interface meets the DC and AC specifications.

If your system has the flexibility to accommodate a selection of driver strengths, you can also use the driver selection guideline to select the appropriate driver without using termination.

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