AN 447: Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

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ID 683295
Date 3/28/2022
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Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems x
Receiver Level Requirements Guideline: Use Internal PCI Clamp Diode on the Pin Guideline: Use Series Termination Resistor Guideline: Select Appropriate Driver Interface Current between Supported Intel® Devices Document Revision History for AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Guideline: Use Internal PCI Clamp Diode on the Pin x
Measuring DC Current with PCI Clamp Diode
Guideline: Use Series Termination Resistor x
Selecting Appropriate Series Termination Resistor Value Example of Determining Series Termination Resistor Value
Guideline: Select Appropriate Driver x
Driver Selection Reference Current Limits Measurement Examples Evaluating Interface Using Driver Selection Method
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

Selecting Appropriate Series Termination Resistor Value

The series termination scheme works by introducing a resistor placed in series between the driver and receiver. The driver impedance and series resistance become the total effective driver impedance. The transmission line impedance has to match the driver impedance to minimize reflection and manage overshoot.
Figure 4. Series Termination Scheme


You must perform a simulation to determine the suitable series resistor value for your interface within the allowable tolerance condition. Choosing the appropriate resistor value for series termination is important:

  • If the resistance is too small, the termination may not effectively reduce or eliminate the overshoot.
  • If the resistance is too large, the driver may not sufficiently drive the transmission line and it can result in a stair-step response.
Level Two Title