AN 447: Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

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ID 683295
Date 3/28/2022
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Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems x
Receiver Level Requirements Guideline: Use Internal PCI Clamp Diode on the Pin Guideline: Use Series Termination Resistor Guideline: Select Appropriate Driver Interface Current between Supported Intel® Devices Document Revision History for AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Guideline: Use Internal PCI Clamp Diode on the Pin x
Measuring DC Current with PCI Clamp Diode
Guideline: Use Series Termination Resistor x
Selecting Appropriate Series Termination Resistor Value Example of Determining Series Termination Resistor Value
Guideline: Select Appropriate Driver x
Driver Selection Reference Current Limits Measurement Examples Evaluating Interface Using Driver Selection Method
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

Interface Current between Supported Intel® Devices

The supported Intel® devices can drive into each other without termination for certain drive strengths using the 3.3 V, 3.0 V, or 2.5 V LVTTL or LVCMOS I/O standards.
Table 3.  Interface Current Between Supported Intel® Devices Without Additional SolutionIn this table, "Yes" means that you can drive into the supported Intel® device receiver unterminated—with the I/O standard drive strengh and corresponding bank VCCIO—without violating the DC and AC input voltage specifications.
Driver I/O Standard Drive Strength Receiver Bank VCCIO(V)3
2.5 ± 5% 3.0 ± 5% 3.3 ± 5%
2.5 V LVTTL 4 mA Yes Yes Yes
8 mA Yes Yes Yes
12 mA Yes Yes —
16 mA Yes Yes —
3.0 V LVTTL 4 mA Yes Yes Yes
8 mA Yes Yes Yes
12 mA — Yes —
16 mA — Yes —
3.0 V LVCMOS 4 mA Yes Yes Yes
8 mA — Yes —
12 mA — Yes —
16 mA — Yes —
3.3 V LVTTL 4 mA Yes Yes Yes
8 mA 4 Yes Yes
3.3 V LVCMOS 2 mA 4 Yes Yes
3 The Intel® Quartus® Prime software enables the PCI clamp diode for pins assigned as 3.3 V, 3.0 V, or 2.5 V LVTTL or LVCMOS I/O standards by default.
4 With the PCI clamp diode enabled, the supported Intel® devices—at this I/O standard, drive strength, and receiver bank VCCIO combination—cannot drive each other unterminated. To use this combination without violating the specifications, disable the PCI clamp diode.
Level Two Title