Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

7.2.3. SystemVerilog Interface Properties

Name Description
SV_INTERFACE_TYPE Set the interface type of the SystemVerilog interface.
USE_ALL_PORTS

When USE_ALL_PORTS is set to true, all the ports defined in the Module, are declared in this SystemVerilog interface.

USE_ALL_PORTS must be set to true only if the module has one SystemVerilog interface and the SystemVerilog interface signal names match with the port names declared for Platform Designer interface.

When USE_ALL_PORTS is true, SV_INTERFACE_PORT or SV_INTERFACE_SIGNAL port properties should not be set.