Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

ID 683551
Date 4/30/2024
Public
Document Table of Contents

2.2.3.2. Clocking Scheme

Figure 15. Clocking Scheme for 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver