Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

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ID 683551
Date 4/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 2.1.4. Compiling and Configuring the Design Example in Hardware
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench x
2.1.3.1. Procedure
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Hardware Testing 2.2.6. Interface Signals 2.2.7. Configuration Registers
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clocking Scheme
2.2.5. Hardware Testing x
2.2.5.1. Test Procedure
2.2.7. Configuration Registers x
2.2.7.1. Register Access Definition 2.2.7.2. Triple-Speed Ethernet Register Map 2.2.7.3. Traffic Controller Register Map 2.2.7.4. TOD Register Map
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

2.2.3.1. Design Components

Table 9.  Design Components
Component Description
Triple-Speed Ethernet Intel® FPGA IP

The Triple-Speed Ethernet Intel® FPGA IP is instantiated with the following configuration:

  • Core Configurations:
    • Core Variation: 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS
    • Use internal FIFO: Not selected
    • Transceiver type: None
  • MAC Options:
    • Include statistics counters: Selected
    • Enable magic packet detection: Selected
  • PCS/Transceiver Options:
    • Enable SGMII bridge: Selected
  • Timestamp Options:
    • Enable timestamping: Selected
    • Enable deterministic latency for E-tile device: Selected
    • Enable PTP 1-step clock: Selected
    • Timestamp fingerprint width: 4
E-Tile PMA The Stratix® 10 E-tile Transceiver Native PHY IP is instantiated with the following configuration:
  • Datapath Options:
    • Transceiver configuration rules: PMA direct
    • Transceiver mode: TX/RX Duplex
    • Number of data channels: 1
  • TX PMA Options:
    • TX PMA modulation type: NRZ
    • TX PMA data rate: 1250
    • TX PMA reference clock frequency: 156.25MHz
  • RX PMA Options:
    • RX PMA modulation type: NRZ
    • RX PMA data rate: 1250
    • Enable RX PMA div66 clock: Selected
    • Enable RX PMA full-rate clock: Selected
    • RX PMA reference clock frequency: 156.25MHz
    • Enable rx_is_lockedtodata port: Selected
  • Core Interface Options:
    • TX Core interface FIFO mode: Phase compensation
    • TX Core interface FIFO partially full threshold: 5
    • TX Core interface FIFO partially empty threshold: 2
    • Enable TX double width transfer: Not selected
    • RX Core interface FIFO mode: Phase compensation
    • RX Core interface FIFO partially full threshold: 5
    • RX Core interface FIFO partially empty threshold: 2
    • Enable RX double width transfer: Not selected
    • Selected tx_clkout clock source: full-rate
    • Selected rx_clkout clock source: full-rate
    • Enable latency measurement ports: Selected
    • Enable latency measurement feature: Selected
  • PMA Interface Options:
    • TX PMA interface width: 20
    • RX PMA interface width: 20
Design Components for the IEEE 1588v2 Feature
TX IOPLL Upstream

Generates the reference clock source for TX IOPLL.

This is because there is a PTP requirement that the TX datapath clocks must meet the 0 ppm criteria.

TX IOPLL Generates TX datapath 125 MHz and 62.5 MHz clocks for Triple-Speed Ethernet.
RX IOPLL Generates RX datapath 125 MHz and 62.5 MHz clocks for Triple-Speed Ethernet.
TOD and DL IOPLL Generates TOD sampling clock and DL sampling clock.
Master TOD Master TOD.
TOD synchronizer Synchronizes master TOD to the TX and RX TOD.
TX TOD TX TOD to provide the TOD value for TX timestamp calculation.
RX TOD RX TOD to provide the TOD value for RX timestamp calculation.
PTP Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information to the Triple-Speed Ethernet Intel® FPGA IP.
Traffic Controller Generates and monitors packets transmission in the design example.
Level Two Title