Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

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ID 683551
Date 4/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 2.1.4. Compiling and Configuring the Design Example in Hardware
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench x
2.1.3.1. Procedure
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Hardware Testing 2.2.6. Interface Signals 2.2.7. Configuration Registers
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clocking Scheme
2.2.5. Hardware Testing x
2.2.5.1. Test Procedure
2.2.7. Configuration Registers x
2.2.7.1. Register Access Definition 2.2.7.2. Triple-Speed Ethernet Register Map 2.2.7.3. Traffic Controller Register Map 2.2.7.4. TOD Register Map
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

2.2.7.3. Traffic Controller Register Map

The traffic controller consists of the packet generator and the traffic monitor.
Table 17.  Packet Generator Register Map
Byte Offset R/W Name Description HW Reset
0x00 RW NUMPKTS The total number of Ethernet packets that the traffic generator generates and transmits to the design components. 0
0x04 RW RANDOMLENGTH

Enables random packet length up to the value of the PKTLENGTH register.

  • 0x00: Fixed length.
  • 0x01: Random length.
 0
0x08 RW RANDOMPAYLOAD

Enables random contents of the payload.

  • 0x00: Incremental.
  • 0x01: Random.
 0
0x0C RW START Start the generation of the Ethernet traffic by writing 0x01 to this register. 0
0x10 RW STOP Stops the generation of the Ethernet traffic by writing 0x01 to this register. 0
0x14 RW MACSA0 The lower 32 bits of the source address. 0
0x18 RW MACSA1 The upper 16 bits of the source address. The remaining 16 bits are not used. 0
0x1C RW MACDA0 The lower 32 bits of the destination address. 0
0x20 RW MACDA1 The upper 16 bits of the source address. The remaining 16 bits are not used. 0
0x24 RO TXPKTCNT The number of packets that the traffic generator transmitted. Read this register when the traffic generator is not active, for example, when the testing has completed. 0
0x34 RW PKTLENGTH When random-sized packets are enabled, this register specifies the maximum payload length. Otherwise, it specifies the length of the packet to be generated. 0
Table 18.  Traffic Monitor Register Map
Byte Offset R/W Name Description HW Reset
0x00 RW RXPKTCNT_EXPT The number of packets that the traffic monitor expects to receive. 0xFFFFFFFF
0x04 RO RXPKTCNT_GOOD The number of good packets received by the traffic monitor. 0
0x08 RO RXPKTCNT_BAD The number of packets received with CRC error. 0
0x0C RO RXBYTECNT_LO32 The lower 32 bits of the counter that keeps track of the total number of bytes the traffic monitor received. 0
0x10 RO RXBYTECNT_HI32 The upper 32 bits of the counter that keeps track of the total number of bytes the traffic monitor received. 0
0x14 RO RXCYCLCNT_LO32 The lower 32-bit of the counter that keeps track of the total number of clock cycles required by the traffic monitor to receive the expected number of packets. 0
0x18 RO RXCYCLCNT_HI32 The upper 32-bit of the counter that keeps track of the total number of clock cycles required by the traffic monitor to receive the expected number of packets. 0
0x1C RW RXCTRL_STATUS

Monitors the configuration and status register.

  • Bit [0]: Set to 1 to initialize all of the traffic monitor counters.
  • Bit [1]: Reserved.
  • Bit [2]: When set to 1, indicates that the traffic monitor has received the total number of expected packets. This bit is a read-only bit.
  • Bits [31:3]: Reserved.
 0
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