Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.7.1. Intel Arria 10 Remote Update Design Example

This Intel® Arria® 10 design example uses the Avalon® memory-mapped interface. Intel uses the following hardware and software to create the design example:

  • Intel® Quartus® Prime Version: 15.0
  • Intel® Arria® 10 Development Kit with 10AX115S3F45I2SGE2 FPGA Device

Follow these steps to perform the design example tasks:

  1. Unzip the contents of the design example to your working directory on your PC.
  2. Convert the three .sof files into one .jic by using Convert Programming File. On the File Menu, click Convert Programming Files and select the details as shown below:
    • Programming File type: JTAG Indirect Configuration File (.jic).
    • Select Configuration Device: EPCQL1024.
    • Mode: Active Serial.
    • Set the file name you your desired location.
    • Flash loader: click add device and choose 10AX115S2E2.
    • SOFT DATA PAGE_0: click Add File and select the factory image with start address set to <auto>.
    • SOFT DATA PAGE_1: click Add File and select the application image file with start address 0x2000000. Compression is enabled for this application image file.
    • SOFT DATA PAGE_2: click Add File and select the application image file with start address 0x4000000. Compression is enabled for this application image file.
    • Click Generate.
    • Click OK when the dialog box of .jic file successfully generated appears.
  3. Please follow the steps below to run the simple design:
    1. After programming the .jic file, power cycle the board, all LEDs are lighted up. It indicates you are currently at factory image.
    2. Go to system console and direct to the directory where your FI_SysConsole_try.tcl is located. Type source FI_SysConsole_try.tcl.
    Only one LED is lighted up which indicates successfully go to application image 1. After the watchdog timeout, all LEDs are lighted up and go back to factory image.
    Note: To go to application image 2 directly form the factory image, comment out the write boot address to App1 and uncomment the write boot address App2 in the FI_SysConsole_try.tcl file.
  4. Setting Boot Page Selection for design with more than one SOF page:
    1. To select the boot page, click the Option/Boot Info button in Convert Programming File.
    2. In the Active Serial Boot Info window, select the page available from the Boot from page drop down menu. By default, the page number is set at page_0.
    3. For application to application image, change the page number to page_1 or page_2.
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