Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.5.7.2. Register Map

Table 21.  Remote Update Intel® FPGA IP Core Avalon® -MM Register Map for Cyclone® IV and Intel® Cyclone® 10 LP Devices
  • The last two bits of an address represents the read_source signals.
  • You have to write the correct address offset to carry read_source value as shown in the Read Source Mapping table.
  • The IP core combines the address bus of control status register interface to the read_source parameter.
  • The default value for the registers is 0.
  • The address offsets are in word.
Register Name Address Offset Width R/W Description
RU_MASTER_SM_CURRENT_STATE_MODE 0x0 2 Read

Read current state of the state machine

00: Factory mode

01: Application mode

11: Application mode with the master state machine user watchdog timer enabled.

RU_FORCE_EARLY_CONF_DONE 0x4 1 Read/Write Force early CONF_DONE
RU_WATCHDOG_TIMEOUT 0x8 29 or 12 Read/Write Read or write watchdog timeout value.
  • 12 bit wide when writing
  • 29 bit wide when reading
RU_WATCHDOG_ENABLE 0xC 1 Read/Write Enable or disable watchdog timeout.
  • 0: Disable
  • 1: Enable
 
RU_BOOT_ADDRESS
 0x10 24, 29 or 32 Read/Write
  • 29 or 32 bit wide (EPCQ 32 bit addressing) when reading boot address.
  • 24 or 32 bit wide when writing the boot address.
RU_FORCE_INTERNAL_OSC 0x14 1 Read/Write Force the internal oscillator as startup state machine clock (osc_int) option bit
RU_RECONFIG_TRIGGER_CONDITIONS 0x18 5 Read Read configuration trigger conditions.
  • Bit 4—nconfig_source: External configuration reset (nCONFIG) assertion.
  • Bit 3—crcerror_source: CRC error during application configuration.
  • Bit 2—nstatus_source: nSTATUS asserted by an external device as the result of an error
  • Bit 1—wdtimer_source: Users watchdog timer timeout
  • Bit 0—runconfig_source: Configuration reset triggered from logic array
RU_RESET_TIMER 0x1C 1 Write

Write a value of 1 to this register to trigger reset timer of the remote update. The IP core will automatically trigger a reset pulse to reset timer pin of the remote update.

RU_RECONFIG 0x1D 1 Write

Write to this address with value of 1 to trigger reconfiguration from a new image. The IP core will set 1 to reconfig pin of the remote update and hold this value until the process done.

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