Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.5.5. Parameters

Table 17.  Parameter Type and Corresponding Parameter Bit Width Mapping for Cyclone® IV and Intel® Cyclone® 10 LP Devices
Bit Parameter Width Comments
000 Master State Machine Current State Mode (Read Only) 2

00—Factory mode.

01—Application mode.

11—Application mode with the master state machine user watchdog timer enabled.

001 Force early CONF_DONE (cd_early) check 1 —
010 Watchdog Timeout Value 12 Width of 12 when writing.

The 12 bits for writing are the upper 12 bits (left-most or most-significant bits) of the 29-bit Watchdog Timeout Value.

When writing parameter data, data_in[11..0] corresponds to the upper 12 bits of the 29-bit Watchdog Timeout Value. For example, to set the Watchdog Timeout Value to 1, write the 12 bits of data_in[11..0] as 12'b000000000001.

29 Width of 29 when reading.
011 Watchdog Enable 1 —
100 Boot Address —

For the Intel® Quartus® Prime software version 13.1 and later:

  • Width of 29 or 32 when reading the boot address.
  • Width of 24 or 32 when writing the boot address.
  • For active serial devices using the 24-bit addressing, such as EPCS128 or EPCQ128, boot_address[23..2] corresponds to the upper 22 bits of the 24-bits boot address. boot_address[1..0] is read as 2'b0.
  • For active serial devices using the 32-bit addressing, such as EPCQ256, boot_address[31..2] corresponds to the upper 30 bits of the 32-bits boot address. boot_address[1..0] is read as 2'b0.

For the Intel® Quartus® Prime software version 13.0 or earlier:

  • Width of 24 when reading the boot address.
  • Width of 22 when writing the boot address.
  • Writes the boot address to the upper 22 bits of the 24-bits boot address.
101 Illegal Value
110 Force the internal oscillator as startup state machine clock (osc_int) option bit 1 —
111 Reconfiguration trigger conditions (Read Only) 5

Bit 4 (nconfig_source)—external configuration reset (nconfig) assertion.

Bit 3 (crcerror_source)—CRC error during application configuration.

Bit 2 (nstatus_source)—nstatus asserted by an external device as the result of an error.

Bit 1 (wdtimer_source)—User watchdog timer timeout.

Bit 0 (runconfig_source)—Configuration reset triggered from logic array.

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