Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.3.4. Ports

Table 4.  Remote Update Intel® FPGA IP Core Ports for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Name Port Required? Description
read_param Input No

Read signal for the parameter specified in param[] input port and fed to data_out[] output port.

Signal indicating the parameter specified on the param[] port should be read. The number of bits set on data_out[] depends on the parameter type. The signal is sampled at the rising clock edge. Assert the signal for only one clock cycle to prevent the parameter from being read again in a subsequent clock cycle.

The busy signal is activated as soon as read_param is read as active. While the parameter is being read, the busy signal remains asserted, and data_out[] has invalid data. When the busy signal is deactivated and data_out[] has a valid data, another parameter can be read.

write_param Input No

Write signal for parameter specified in param[] and with value specified in data_in[].

Signal indicating parameter specified with param[] should be written into remote update block with the value specified in data_in[]. The number of bits read from data_in[] depends on the parameter type.

The signal is sampled at the rising clock edge. The signal should be asserted for only one clock cycle to prevent the parameter from being rewritten on a subsequent clock cycle. The busy signal is activated as soon as write_param is read as being active. While the parameter is being written, the busy signal remains asserted, and input to data_ in[] is ignored. When the busy signal is deactivated, another parameter can be written. This signal is only valid in factory configuration mode because parameters cannot be written in Application configuration mode.

param[] Input No

Bus that specifies which parameter need to be read or updated.

A 3-bit bus that selects the parameter to be read or updated. If left unconnected, the default value for this port is 000.

data_in[] Input No

Data input for writing parameter data into the remote update block. Input bus for parameter data.

For some parameters, not all bits are used. In this case, the lower-order bits are used (for example, status values use bits [4:0]).

If left unconnected, this bus defaults to 0. The port is ignored if the current configuration is the Application configuration.

A 32-bit bus width (4-bytes addressing configuration device, for example EPCQ-L256) in the Intel® Quartus® Prime software version 14.0 or later.

reconfig Input Yes

Signal indicating that reconfiguration of the part should begin using the current parameter settings. A value of 1 indicates reconfiguration should begin. This signal is ignored if the busy signal is asserted to ensure all parameters are completely written before reconfiguration begins.

reset_timer Input

No

Reset signal for watchdog timer.

Signal indicating the internal watchdog timer should be reset. Unlike other inputs, this signal is not affected by the busy signal and can reset the timer even when the busy signal is asserted.

A falling edge of this signal triggers a reset of the user watchdog timer.

For the timing specification of this parameter, refer to the specific device handbook.

clock

Input Yes

Clock input to the remote update block.

Clock input to control the machine and to drive the remote update block during the update of parameters.

This port must be connected to a valid clock.
reset Input Yes

This is an active high signal. Asserting this signal high will reset the IP core.

Asynchronous reset input to the IP core to initialize the machine to a valid state. The machine must be reset before first use, otherwise the state is not guaranteed to be valid.

busy Output No

Busy signal that indicates when remote update block is reading or writing data.

While this signal is asserted, the machine ignores most of its inputs and cannot be altered until the machine deasserts this signal. Therefore, changes are made only when the machine is not busy.

This signal goes high when read_param or write_ param is asserted, and remains high until the read or write operation completes.

data_out[] Output No

Data output when reading parameters.

This bus holds read parameter data from the remote update block. The param[] value specifies the parameter to read. When the read_param signal is asserted, the parameter value is loaded and driven on this bus. Data is valid when the busy signal is deasserted.

If left unconnected, the default value for the port is 0.

The width of this bus is device-dependent. For the Intel® Quartus® Prime software version 14.0 and later, the bus width is 32-bit—using 4-byte addressing configuration device, for example EPCQL-256.

ctl_nupdt Input Yes

This port allows you to select which register to be read whenever read_param operation is running.

  • A logic high selects the Control Register—register containing the current remote update settings such as watchdog timer settings, configuration mode (AnF), and page address.
  • A logic low selects the Update Register—register containing similar data as held in the Control Register, but the values are updated via write_param operation for use in next reconfiguration.
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