RapidIO Intel FPGA IP User Guide

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ID 683884
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the RapidIO Intel FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Signals 6. Software Interface 7. Testbench 8. Platform Designer (Standard) Design Example 9. RapidIO Intel FPGA IP User Guide Archives 10. Document Revision History for the RapidIO Intel® FPGA IP User Guide A. Initialization Sequence B. Porting a RapidIO Design from the Previous Version of Software
1. About the RapidIO Intel FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grades 1.6. Release Information
1.1. Features x
1.1.1. Supported Transactions
1.3. IP Core Verification x
1.3.1. Simulation Testing 1.3.2. Hardware Testing 1.3.3. Interoperability Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generating IP Cores 2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition) 2.4. RapidIO IP Core Testbench Files 2.5. Simulating IP Cores 2.6. Integrating Your IP Core in Your Design 2.7. Specifying Timing Constraints 2.8. Compiling the Full Design and Programming the FPGA 2.9. Instantiating Multiple RapidIO IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Generating IP Cores x
2.2.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.5. Simulating IP Cores x
2.5.1. Simulating the Testbench with the ModelSim Simulator 2.5.2. Simulating the Testbench with the VCS Simulator 2.5.3. Simulating the Testbench with the Xcelium Simulator
2.6. Integrating Your IP Core in Your Design x
2.6.1. Calibration Clock 2.6.2. Dynamic Transceiver Reconfiguration Controller 2.6.3. Transceiver Settings 2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations 2.6.5. External Transceiver PLL 2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9. Instantiating Multiple RapidIO IP Cores x
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations 2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations 2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances 2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
3. Parameter Settings x
3.1. Physical Layer Settings 3.2. Transport and Maintenance Settings 3.3. I/O and Doorbell Settings 3.4. Capability Registers Settings
3.1. Physical Layer Settings x
3.1.1. Device Options 3.1.2. Data Settings 3.1.3. Receive Priority Retry Thresholds 3.1.4. Transceiver Settings
3.2. Transport and Maintenance Settings x
3.2.1. Transport Layer 3.2.2. Input/Output Maintenance Logical Layer Module 3.2.3. Port Write
3.3. I/O and Doorbell Settings x
3.3.1. I/O Logical Layer Interfaces 3.3.2. I/O Slave Address Width 3.3.3. I/O Read and Write Order Preservation 3.3.4. Avalon® -MM Master 3.3.5. Avalon® -MM Slave 3.3.6. Doorbell Slave
3.4. Capability Registers Settings x
3.4.1. Device Registers 3.4.2. Assembly Registers 3.4.3. Processing Element Features 3.4.4. Switch Support 3.4.5. Data Messages
4. Functional Description x
4.1. Interfaces 4.2. Clocking and Reset Structure 4.3. Physical Layer 4.4. Transport Layer 4.5. Logical Layer Modules 4.6. Error Detection and Management
4.1. Interfaces x
4.1.1. RapidIO Interface 4.1.2. Avalon® Memory Mapped ( Avalon® -MM) Master and Slave Interfaces 4.1.3. Avalon® Streaming ( Avalon® -ST) Interface
4.1.2. Avalon® Memory Mapped ( Avalon® -MM) Master and Slave Interfaces x
4.1.2.1. Avalon® -MM Interface Widths in the RapidIO IP Core 4.1.2.2. Avalon® -MM Interface Byte Ordering
4.2. Clocking and Reset Structure x
4.2.1. RapidIO IP Core Clocking 4.2.2. Reset for RapidIO IP Cores
4.2.1. RapidIO IP Core Clocking x
4.2.1.1. Avalon® System Clock 4.2.1.2. Reference Clock 4.2.1.3. Other Input Clocks 4.2.1.4. Clock Domains 4.2.1.5. Baud Rates and Clock Frequencies
4.2.2. Reset for RapidIO IP Cores x
4.2.2.1. General RapidIO Reset Signal Requirements 4.2.2.2. Reset Controller 4.2.2.3. Reset Requirements for Arria® V, Cyclone® V, and Stratix® V Variations 4.2.2.4. Reset Requirements for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations 4.2.2.5. RapidIO IP Core Reset Behavior
4.3. Physical Layer x
4.3.1. Features 4.3.2. Physical Layer Architecture 4.3.3. Low-level Interface Receiver 4.3.4. Low-Level Interface Transmitter 4.3.5. Protocol and Flow Control Engine 4.3.6. Physical Layer Receive Buffer 4.3.7. Physical Layer Transmit Buffer
4.3.3. Low-level Interface Receiver x
4.3.3.1. Receiver Transceiver 4.3.3.2. CRC Checking and Removal
4.3.4. Low-Level Interface Transmitter x
4.3.4.1. Transmitter Transceiver
4.3.6. Physical Layer Receive Buffer x
4.3.6.1. Error Conditions that Flush the Receive Buffer 4.3.6.2. Error Conditions Flagged for the Transport Layer 4.3.6.3. Receive Priority Threshold Values
4.3.7. Physical Layer Transmit Buffer x
4.3.7.1. Transmit and Retransmit Queues 4.3.7.2. Error Conditions that Flush the Transmit Buffer 4.3.7.3. Forced Compensation Sequence Insertion
4.4. Transport Layer x
4.4.1. Receiver 4.4.2. Transaction ID Ranges 4.4.3. Transmitter
4.5. Logical Layer Modules x
4.5.1. Concentrator Register Module 4.5.2. Maintenance Module 4.5.3. Input/Output Logical Layer Modules 4.5.4. Doorbell Module 4.5.5. Avalon® -ST Pass-Through Interface
4.5.2. Maintenance Module x
4.5.2.1. Maintenance Register 4.5.2.2. Maintenance Slave Processor 4.5.2.3. Maintenance Master Processor 4.5.2.4. Port-Write Processor 4.5.2.5. Maintenance Module Error Handling
4.5.2.4. Port-Write Processor x
4.5.2.4.1. Port-Write Transmission 4.5.2.4.2. Port-Write Reception
4.5.3. Input/Output Logical Layer Modules x
4.5.3.1. Input/Output Avalon® -MM Master Module 4.5.3.2. Input/Output Avalon® -MM Master Module Timing Diagrams 4.5.3.3. Input/Output Avalon® -MM Slave Module 4.5.3.4. Avalon® -MM Burstcount and Byteenable Encoding in RapidIO Packets 4.5.3.5. Input/Output Avalon® -MM Slave Module Timing Diagrams
4.5.3.1. Input/Output Avalon® -MM Master Module x
4.5.3.1.1. Input/Output Avalon® -MM Master Address Mapping Windows
4.5.3.3. Input/Output Avalon® -MM Slave Module x
4.5.3.3.1. Keeping Track of I/O Write Transactions 4.5.3.3.2. Input/Output Avalon® -MM Slave Address Mapping Windows 4.5.3.3.3. Input/Output Slave Translation Window Example 4.5.3.3.4. Translation Window 0 4.5.3.3.5. Translation Window 1 4.5.3.3.6. Translation Window 2
4.5.4. Doorbell Module x
4.5.4.1. Doorbell Module Block Diagram 4.5.4.2. Preserving Transaction Order 4.5.4.3. Doorbell Message Generation 4.5.4.4. Doorbell Message Reception
4.5.5. Avalon® -ST Pass-Through Interface x
4.5.5.1. Pass-Through Interface Examples
4.6. Error Detection and Management x
4.6.1. Physical Layer Error Management 4.6.2. Logical Layer Error Management 4.6.3. Avalon® -ST Pass-Through Interface
4.6.1. Physical Layer Error Management x
4.6.1.1. Protocol Violations 4.6.1.2. Fatal Errors
4.6.2. Logical Layer Error Management x
4.6.2.1. Maintenance Avalon® -MM Slave 4.6.2.2. Maintenance Avalon® -MM Master 4.6.2.3. Port-Write Reception Module 4.6.2.4. Port-Write Transmission Module 4.6.2.5. Input/Output Avalon® -MM Slave 4.6.2.6. Input/Output Avalon® -MM Master
4.6.2.1. Maintenance Avalon® -MM Slave x
4.6.2.1.1. Standard Error Management Registers 4.6.2.1.2. Registers in the Implementation Defined Space 4.6.2.1.3. Maintenance Avalon® -MM Slave Interface's Error Indication Signal
4.6.2.5. Input/Output Avalon® -MM Slave x
4.6.2.5.1. Standard Error Management Registers 4.6.2.5.2. Registers in the Implementation Defined Space 4.6.2.5.3. The Avalon® -MM Slave Interface's Error Indication Signal
4.6.2.6. Input/Output Avalon® -MM Master x
4.6.2.6.1. Standard Error Management Registers 4.6.2.6.2. Response Packets with ERROR Status
5. Signals x
5.1. Physical Layer Signals 5.2. Transport and Logical Layer Signals
5.1. Physical Layer Signals x
5.1.1. Status Packet and Error Monitoring Signals 5.1.2. Multicast Event Signals 5.1.3. Receive Priority Retry Threshold-Related Signals 5.1.4. Physical Layer Buffer Status Signals 5.1.5. Transceiver Signals 5.1.6. Register-Related Signals
5.2. Transport and Logical Layer Signals x
5.2.1. Avalon® -MM Interface Signals 5.2.2. Avalon® -ST Pass-Through Interface Signals 5.2.3. Error Management Extension Signals 5.2.4. Packet and Error Monitoring Signal for the Transport Layer
6. Software Interface x
6.1. Physical Layer Registers 6.2. Transport and Logical Layer Registers
6.2. Transport and Logical Layer Registers x
6.2.1. Capability Registers (CARs) 6.2.2. Command and Status Registers (CSRs) 6.2.3. Maintenance Interrupt Control Registers 6.2.4. Receive Maintenance Registers 6.2.5. Transmit Maintenance Registers 6.2.6. Transmit Port-Write Registers 6.2.7. Receive Port-Write Registers 6.2.8. Input/Output Master Address Mapping Registers 6.2.9. Input/Output Slave Mapping Registers 6.2.10. Input/Output Slave Interrupts 6.2.11. Transport Layer Feature Register 6.2.12. Error Management Registers 6.2.13. Doorbell Message Registers
7. Testbench x
7.1. Reset, Initialization, and Configuration 7.2. Maintenance Write and Read Transactions 7.3. SWRITE Transactions 7.4. NWRITE_R Transactions 7.5. NWRITE Transactions 7.6. NREAD Transactions 7.7. Doorbell Transactions 7.8. Doorbell and Write Transactions With Transaction Order Preservation 7.9. Port-Write Transactions 7.10. Transactions Across the Avalon® -ST Pass-Through Interface
8. Platform Designer (Standard) Design Example x
8.1. Creating a New Intel® Quartus® Prime Project 8.2. Running Platform Designer (Standard) 8.3. Simulating the System
8.2. Running Platform Designer (Standard) x
8.2.1. Adding and Parameterizing the RapidIO Component 8.2.2. Adding and Connecting Other System Components 8.2.3. Connecting Clocks and the System Components 8.2.4. Generating the System
8.2.2. Adding and Connecting Other System Components x
8.2.2.1. Adding the Master Maintenance BFM 8.2.2.2. Adding the Master I/O BFM 8.2.2.3. Adding the On-Chip Memory
8.2.3. Connecting Clocks and the System Components x
8.2.3.1. Connecting Unconnected Clocks 8.2.3.2. Connecting System Components 8.2.3.3. Assigning Addresses and Setting the Clock Frequency
B. Porting a RapidIO Design from the Previous Version of Software x
B.1. Upgrading a RapidIO Design Without Changing Device Family B.2. Upgrading a RapidIO Design to the Intel® Arria® 10 and Intel® Cyclone® 10 GX Device Families
Product Discontinuance Notification
1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software

5.2.1. Avalon® -MM Interface Signals

Signals on Avalon® -MM interfaces are in the Avalon® system clock domain.
When you instantiate the IP core in Platform Designer (Standard), these signals are automatically connected and are not visible as inputs or outputs of the system.
Table 42.  System Maintenance Avalon® -MM Slave Interface Signals
Signal Direction Description
sys_mnt_s_clk Input This signal is not used, therefore it can be left open. The Avalon® clock is used internally to sample this interface.
sys_mnt_s_chipselect Input System maintenance slave chip select
sys_mnt_s_waitrequest Output System maintenance slave wait request
sys_mnt_s_read Input System maintenance slave read enable
sys_mnt_s_write Input System maintenance slave write enable
sys_mnt_s_address[16:0] Input System maintenance slave address bus. This address is a word address (addresses a 4-byte (32-bit) word), not a byte address.
sys_mnt_s_writedata[31:0] Input System maintenance slave write data bus
sys_mnt_s_readdata[31:0] Output System maintenance slave read data bus
sys_mnt_s_irq Output System maintenance slave interrupt request
Table 43.  Maintenance Avalon® -MM Master Interface Signals
Signal Direction Description
mnt_m_clk Input This signal is not used, therefore it can be left open. The Avalon® clock is used internally to sample this interface.
mnt_m_waitrequest Input Maintenance master wait request
mnt_m_read Output Maintenance master read enable
mnt_m_write Output Maintenance master write enable
mnt_m_address[31:0] Output Maintenance master address bus
mnt_m_writedata[31:0] Output Maintenance master write data bus
mnt_m_readdata[31:0] Input Maintenance master read data bus
mnt_m_readdatavalid Input Maintenance master read data valid
Table 44.  Maintenance Avalon® -MM Slave Interface Signals
Signal Direction Description
mnt_s_clk Input This signal is not used, therefore it can be left open. The Avalon® clock is used internally as the clock reference for this interface.
mnt_s_chipselect Input Maintenance slave chip select.
mnt_s_waitrequest Output Maintenance slave wait request.
mnt_s_read Input Maintenance slave read enable.
mnt_s_write Input Maintenance slave write enable.
mnt_s_address[23:0] Input Maintenance slave address bus. This address is a word address (addresses a 4-byte (32-bit) word), not a byte address.
mnt_s_writedata[31:0] Input Maintenance slave write data bus.
mnt_s_readdata[31:0] Output Maintenance slave read data bus.
mnt_s_readdatavalid Output Maintenance slave read data valid.
mnt_s_readerror Output Maintenance slave read error, which indicates that the read transfer did not complete successfully. This signal is valid only when the mnt_s_readdatavalid signal is asserted.

The following parameters are used in some signal width definitions:

  • n = (internal datapath width - 1)
  • m = (internal datapath width/8) - 1
  • k = 6 for 32-bit internal datapath width, and 5 for 64-bit internal datapath width
  • j = ((I/O slave address width minus N) - 1) — the I/O slave address width value is defined in the RapidIO parameter editor. N is 2 for 1x variations and 3 for 2x and 4x variations.

The internal datapath width is 32 bits in RapidIO 1x variations, and 64 bits in RapidIO 2x and 4x variations.

Table 45.  Input/Output Master Datapath Write Avalon® -MM Interface Signals
Signal Direction Description
io_m_wr_clk Input This signal is not used, therefore it can be left open. The Avalon® clock is used internally as the clock reference for this interface.
io_m_wr_waitrequest Input Input/Output master wait request.
io_m_wr_write Output Input/Output master write enable.
io_m_wr_address[31:0] Output Input/Output master address bus.
io_m_wr_writedata[n:0] Output Input/Output master write data bus.
io_m_wr_byteenable[m:0] Output Input/Output master byte enable.
io_m_wr_burstcount[k:0] Output Input/Output master burst count.
Table 46.  Input/Output Master Datapath Read Avalon® -MM Interface Signals
Signal Direction Description
io_m_rd_clk Input This signal is not used, therefore it can be left open. The Avalon® clock is used internally as the clock reference for this interface.
io_m_rd_waitrequest Input Input/Output master wait request.
io_m_rd_read Output Input/Output master read enable.
io_m_rd_address[31:0] Output Input/Output master address bus.
io_m_rd_readdata[n:0] Input Input/Output master read data bus.
io_m_rd_readdatavalid Input Input/Output master read data valid.
io_m_rd_burstcount[k:0] Output Input/Output master burst count.
io_m_rd_readerror Input Input/Output master indicates that the burst read transfer did not complete successfully. This signal should be asserted through the final cycle of the read transfer.
Table 47.  Input/Output Slave Datapath Write Avalon® -MM Interface Signals
Signal Direction Description
io_s_wr_clk Input This signal is not used, therefore it can be left open. The Avalon® clock is used internally as the clock reference for this interface.
io_s_wr_chipselect Input Input/Output slave chip select.
io_s_wr_waitrequest Output Input/Output slave wait request.
io_s_wr_write Input Input/Output slave write enable.
io_s_wr_address[j:0] Input Input/Output slave address bus. In 1x variations, this address is a word address (addresses a 4-byte (32-bit) word), not a byte address. In 2x and 4x variations, this address is a double-word address (addresses an 8-byte (64-bit) word).
io_s_wr_writedata[n:0] Input Input/Output slave write data bus.
io_s_wr_byteenable[m:0] Input Input/Output slave byte enable.
io_s_wr_burstcount[k:0] Input Input/Output slave burst count.
Table 48.  Input/Output Slave Datapath Read Avalon® -MM Interface Signals
Signal Direction Description
io_s_rd_clk Input This signal is not used, therefore it can be left open. The Avalon® clock is used internally as the clock reference for this interface.
io_s_rd_chipselect Input Input/Output slave chip select.
io_s_rd_waitrequest Output Input/Output slave wait request.
io_s_rd_read Input Input/Output slave read enable.
io_s_rd_address[j:0] Input Input/Output slave address bus. In 1x variations, this address is a word address (addresses a 4-byte (32-bit) word), not a byte address. In 2x and 4x variations, this address is a double-word address (addresses an 8-byte (64-bit) word).
io_s_rd_readdata[n:0] Output Input/Output slave read data bus.
io_s_rd_readdatavalid Output Input/Output slave read data valid.
io_s_rd_burstcount[k:0] Input Input/Output slave burst count.
io_s_rd_readerror Output Input/Output slave read error indicates that the burst read transfer did not complete successfully. This signal is valid only when the io_s_rd_readdatavalid signal is asserted.
Table 49.  Doorbell Message Avalon® -MM Slave Interface Signals
Signal Direction Description
drbell_s_clk Input This signal is not used, therefore it can be left open. The Avalon® clock is used internally as the clock reference for this interface.
drbell_s_chipselect Input Doorbell chip select
drbell_s_write Input Doorbell write enable
drbell_s_read Input Doorbell read enable
drbell_s_address[3:0] Input Doorbell address bus. This address is a word address (addresses a 4-byte (32-bit) word), not a byte address.
drbell_s_writedata[31:0] Input Doorbell write data bus
drbell_s_readdata[31:0] Output Doorbell read data bus
drbell_s_waitrequest Output Doorbell wait request
drbell_s_irq Output Doorbell interrupt
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