RapidIO Intel FPGA IP User Guide

Download PDF
ID 683884
Date 9/15/2021
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. About the RapidIO Intel FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Signals 6. Software Interface 7. Testbench 8. Platform Designer (Standard) Design Example 9. RapidIO Intel FPGA IP User Guide Archives 10. Document Revision History for the RapidIO Intel® FPGA IP User Guide A. Initialization Sequence B. Porting a RapidIO Design from the Previous Version of Software
1. About the RapidIO Intel FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grades 1.6. Release Information
1.1. Features x
1.1.1. Supported Transactions
1.3. IP Core Verification x
1.3.1. Simulation Testing 1.3.2. Hardware Testing 1.3.3. Interoperability Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generating IP Cores 2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition) 2.4. RapidIO IP Core Testbench Files 2.5. Simulating IP Cores 2.6. Integrating Your IP Core in Your Design 2.7. Specifying Timing Constraints 2.8. Compiling the Full Design and Programming the FPGA 2.9. Instantiating Multiple RapidIO IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Generating IP Cores x
2.2.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.5. Simulating IP Cores x
2.5.1. Simulating the Testbench with the ModelSim Simulator 2.5.2. Simulating the Testbench with the VCS Simulator 2.5.3. Simulating the Testbench with the Xcelium Simulator
2.6. Integrating Your IP Core in Your Design x
2.6.1. Calibration Clock 2.6.2. Dynamic Transceiver Reconfiguration Controller 2.6.3. Transceiver Settings 2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations 2.6.5. External Transceiver PLL 2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9. Instantiating Multiple RapidIO IP Cores x
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations 2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations 2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances 2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
3. Parameter Settings x
3.1. Physical Layer Settings 3.2. Transport and Maintenance Settings 3.3. I/O and Doorbell Settings 3.4. Capability Registers Settings
3.1. Physical Layer Settings x
3.1.1. Device Options 3.1.2. Data Settings 3.1.3. Receive Priority Retry Thresholds 3.1.4. Transceiver Settings
3.2. Transport and Maintenance Settings x
3.2.1. Transport Layer 3.2.2. Input/Output Maintenance Logical Layer Module 3.2.3. Port Write
3.3. I/O and Doorbell Settings x
3.3.1. I/O Logical Layer Interfaces 3.3.2. I/O Slave Address Width 3.3.3. I/O Read and Write Order Preservation 3.3.4. Avalon® -MM Master 3.3.5. Avalon® -MM Slave 3.3.6. Doorbell Slave
3.4. Capability Registers Settings x
3.4.1. Device Registers 3.4.2. Assembly Registers 3.4.3. Processing Element Features 3.4.4. Switch Support 3.4.5. Data Messages
4. Functional Description x
4.1. Interfaces 4.2. Clocking and Reset Structure 4.3. Physical Layer 4.4. Transport Layer 4.5. Logical Layer Modules 4.6. Error Detection and Management
4.1. Interfaces x
4.1.1. RapidIO Interface 4.1.2. Avalon® Memory Mapped ( Avalon® -MM) Master and Slave Interfaces 4.1.3. Avalon® Streaming ( Avalon® -ST) Interface
4.1.2. Avalon® Memory Mapped ( Avalon® -MM) Master and Slave Interfaces x
4.1.2.1. Avalon® -MM Interface Widths in the RapidIO IP Core 4.1.2.2. Avalon® -MM Interface Byte Ordering
4.2. Clocking and Reset Structure x
4.2.1. RapidIO IP Core Clocking 4.2.2. Reset for RapidIO IP Cores
4.2.1. RapidIO IP Core Clocking x
4.2.1.1. Avalon® System Clock 4.2.1.2. Reference Clock 4.2.1.3. Other Input Clocks 4.2.1.4. Clock Domains 4.2.1.5. Baud Rates and Clock Frequencies
4.2.2. Reset for RapidIO IP Cores x
4.2.2.1. General RapidIO Reset Signal Requirements 4.2.2.2. Reset Controller 4.2.2.3. Reset Requirements for Arria® V, Cyclone® V, and Stratix® V Variations 4.2.2.4. Reset Requirements for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations 4.2.2.5. RapidIO IP Core Reset Behavior
4.3. Physical Layer x
4.3.1. Features 4.3.2. Physical Layer Architecture 4.3.3. Low-level Interface Receiver 4.3.4. Low-Level Interface Transmitter 4.3.5. Protocol and Flow Control Engine 4.3.6. Physical Layer Receive Buffer 4.3.7. Physical Layer Transmit Buffer
4.3.3. Low-level Interface Receiver x
4.3.3.1. Receiver Transceiver 4.3.3.2. CRC Checking and Removal
4.3.4. Low-Level Interface Transmitter x
4.3.4.1. Transmitter Transceiver
4.3.6. Physical Layer Receive Buffer x
4.3.6.1. Error Conditions that Flush the Receive Buffer 4.3.6.2. Error Conditions Flagged for the Transport Layer 4.3.6.3. Receive Priority Threshold Values
4.3.7. Physical Layer Transmit Buffer x
4.3.7.1. Transmit and Retransmit Queues 4.3.7.2. Error Conditions that Flush the Transmit Buffer 4.3.7.3. Forced Compensation Sequence Insertion
4.4. Transport Layer x
4.4.1. Receiver 4.4.2. Transaction ID Ranges 4.4.3. Transmitter
4.5. Logical Layer Modules x
4.5.1. Concentrator Register Module 4.5.2. Maintenance Module 4.5.3. Input/Output Logical Layer Modules 4.5.4. Doorbell Module 4.5.5. Avalon® -ST Pass-Through Interface
4.5.2. Maintenance Module x
4.5.2.1. Maintenance Register 4.5.2.2. Maintenance Slave Processor 4.5.2.3. Maintenance Master Processor 4.5.2.4. Port-Write Processor 4.5.2.5. Maintenance Module Error Handling
4.5.2.4. Port-Write Processor x
4.5.2.4.1. Port-Write Transmission 4.5.2.4.2. Port-Write Reception
4.5.3. Input/Output Logical Layer Modules x
4.5.3.1. Input/Output Avalon® -MM Master Module 4.5.3.2. Input/Output Avalon® -MM Master Module Timing Diagrams 4.5.3.3. Input/Output Avalon® -MM Slave Module 4.5.3.4. Avalon® -MM Burstcount and Byteenable Encoding in RapidIO Packets 4.5.3.5. Input/Output Avalon® -MM Slave Module Timing Diagrams
4.5.3.1. Input/Output Avalon® -MM Master Module x
4.5.3.1.1. Input/Output Avalon® -MM Master Address Mapping Windows
4.5.3.3. Input/Output Avalon® -MM Slave Module x
4.5.3.3.1. Keeping Track of I/O Write Transactions 4.5.3.3.2. Input/Output Avalon® -MM Slave Address Mapping Windows 4.5.3.3.3. Input/Output Slave Translation Window Example 4.5.3.3.4. Translation Window 0 4.5.3.3.5. Translation Window 1 4.5.3.3.6. Translation Window 2
4.5.4. Doorbell Module x
4.5.4.1. Doorbell Module Block Diagram 4.5.4.2. Preserving Transaction Order 4.5.4.3. Doorbell Message Generation 4.5.4.4. Doorbell Message Reception
4.5.5. Avalon® -ST Pass-Through Interface x
4.5.5.1. Pass-Through Interface Examples
4.6. Error Detection and Management x
4.6.1. Physical Layer Error Management 4.6.2. Logical Layer Error Management 4.6.3. Avalon® -ST Pass-Through Interface
4.6.1. Physical Layer Error Management x
4.6.1.1. Protocol Violations 4.6.1.2. Fatal Errors
4.6.2. Logical Layer Error Management x
4.6.2.1. Maintenance Avalon® -MM Slave 4.6.2.2. Maintenance Avalon® -MM Master 4.6.2.3. Port-Write Reception Module 4.6.2.4. Port-Write Transmission Module 4.6.2.5. Input/Output Avalon® -MM Slave 4.6.2.6. Input/Output Avalon® -MM Master
4.6.2.1. Maintenance Avalon® -MM Slave x
4.6.2.1.1. Standard Error Management Registers 4.6.2.1.2. Registers in the Implementation Defined Space 4.6.2.1.3. Maintenance Avalon® -MM Slave Interface's Error Indication Signal
4.6.2.5. Input/Output Avalon® -MM Slave x
4.6.2.5.1. Standard Error Management Registers 4.6.2.5.2. Registers in the Implementation Defined Space 4.6.2.5.3. The Avalon® -MM Slave Interface's Error Indication Signal
4.6.2.6. Input/Output Avalon® -MM Master x
4.6.2.6.1. Standard Error Management Registers 4.6.2.6.2. Response Packets with ERROR Status
5. Signals x
5.1. Physical Layer Signals 5.2. Transport and Logical Layer Signals
5.1. Physical Layer Signals x
5.1.1. Status Packet and Error Monitoring Signals 5.1.2. Multicast Event Signals 5.1.3. Receive Priority Retry Threshold-Related Signals 5.1.4. Physical Layer Buffer Status Signals 5.1.5. Transceiver Signals 5.1.6. Register-Related Signals
5.2. Transport and Logical Layer Signals x
5.2.1. Avalon® -MM Interface Signals 5.2.2. Avalon® -ST Pass-Through Interface Signals 5.2.3. Error Management Extension Signals 5.2.4. Packet and Error Monitoring Signal for the Transport Layer
6. Software Interface x
6.1. Physical Layer Registers 6.2. Transport and Logical Layer Registers
6.2. Transport and Logical Layer Registers x
6.2.1. Capability Registers (CARs) 6.2.2. Command and Status Registers (CSRs) 6.2.3. Maintenance Interrupt Control Registers 6.2.4. Receive Maintenance Registers 6.2.5. Transmit Maintenance Registers 6.2.6. Transmit Port-Write Registers 6.2.7. Receive Port-Write Registers 6.2.8. Input/Output Master Address Mapping Registers 6.2.9. Input/Output Slave Mapping Registers 6.2.10. Input/Output Slave Interrupts 6.2.11. Transport Layer Feature Register 6.2.12. Error Management Registers 6.2.13. Doorbell Message Registers
7. Testbench x
7.1. Reset, Initialization, and Configuration 7.2. Maintenance Write and Read Transactions 7.3. SWRITE Transactions 7.4. NWRITE_R Transactions 7.5. NWRITE Transactions 7.6. NREAD Transactions 7.7. Doorbell Transactions 7.8. Doorbell and Write Transactions With Transaction Order Preservation 7.9. Port-Write Transactions 7.10. Transactions Across the Avalon® -ST Pass-Through Interface
8. Platform Designer (Standard) Design Example x
8.1. Creating a New Intel® Quartus® Prime Project 8.2. Running Platform Designer (Standard) 8.3. Simulating the System
8.2. Running Platform Designer (Standard) x
8.2.1. Adding and Parameterizing the RapidIO Component 8.2.2. Adding and Connecting Other System Components 8.2.3. Connecting Clocks and the System Components 8.2.4. Generating the System
8.2.2. Adding and Connecting Other System Components x
8.2.2.1. Adding the Master Maintenance BFM 8.2.2.2. Adding the Master I/O BFM 8.2.2.3. Adding the On-Chip Memory
8.2.3. Connecting Clocks and the System Components x
8.2.3.1. Connecting Unconnected Clocks 8.2.3.2. Connecting System Components 8.2.3.3. Assigning Addresses and Setting the Clock Frequency
B. Porting a RapidIO Design from the Previous Version of Software x
B.1. Upgrading a RapidIO Design Without Changing Device Family B.2. Upgrading a RapidIO Design to the Intel® Arria® 10 and Intel® Cyclone® 10 GX Device Families
Product Discontinuance Notification
1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software

6.1. Physical Layer Registers

The offset values are defined by the RapidIO standard.

Table 56.  Physical Layer Register Map
Address Name Description
0x100 PHEAD0 LP-Serial Register Block Header
0x104 PHEAD1 Reserved register
0x120 PLTCTRL Port Link Time-out Control CSR
0x124 PRTCTRL Port Response Time-out Control CSR
0x13C PGCTRL Port General Control CSR
0x158 ERRSTAT Port 0 Error and Status CSR
0x15C PCTRL0 Port 0 Control CSR
Table 57.  PHEAD0—LP-Serial Register Block Header—0x100
Field Bits Access Function Default
EF_PTR [31:16] RO Hard-wired pointer to the next block in the data structure, if one exists. The value is set from the ef_ptr input port. ef_ptr
EF_ID [15:0] RO Hard-wired extended features ID. 16'h0001
Table 58.  PHEAD1—Reserved Register—0x104
Field Bits Access Function Default
RSRV [31:0] UR0 Reserved 32’h0
Table 59.  PLTCTRL—Port Link Time-Out Control CSR—0x120
Field Bits Access Function Default
VALUE [31:8] RW Time-out interval value for link-layer event pairs such as the time interval between sending a packet and receiving the corresponding acknowledge control symbol, or between sending a link-request and receiving the corresponding link-response. The duration of the link-response time-out is approximately equal to 4.5 seconds multiplied by the contents of this field, divided by (224 - 1). Note: Avoid time-out values less than 0x000010 because they may not be reliable. 24'hFF_FFFF
RSRV [7:0] UR0 Reserved 8’h0
Table 60.  PRTCTRL—Port Response Time-Out Control CSR—0x124
Field Bits Access Function Default
VALUE [31:8] RW Time-out internal value.
  • Physical layer-only variations: This value is not used by the RapidIO IP core. The contents of this register drive the port_response_timeout output signal.
  • Variations using Logical layers: The duration of the port response time-out for all transactions that require a response—including MAINTENANCE, DOORBELL, NWRITE_R, and NREAD transactions—is approximately equal to 4.5 seconds multiplied by the contents of this field, divided by (224 - 1). Note: Avoid time-out values less than 0x000010 because they may not be reliable. Note: A new value in this field might not propagate quickly enough to be applied to the next transaction. Any packet sent within 64 Avalon® clock cycles of the value change in the register might be sent using the previous time-out value. Note: Avoid changing the value in this field when any packet is waiting to be transmitted or waiting for a response, to ensure that in each FIFO, the pending entries all have the same time-out value.
24'hFF_FFFF
RSRV [7:0] UR0 Reserved 8'h0
Table 61.  Port General Control—Offset: 0x13C
Field Bits Access Function Default
HOST [31] RW A host device is a device that is responsible for system exploration, initialization, and maintenance. Host devices typically initialize agent or slave devices.

'b0 - agent or slave device

'b1 - host device

 1'b0
ENA [30] RW The Master Enable bit controls whether or not a device is allowed to issue requests to the system. If Master Enable is not set, the device may only respond to requests.

'b0 - The processing element cannot issue requests

'b1 - The processing element can issue requests

Variations that use only the Physical layer ignore this bit.

1'b0
DISCOVER [29] RW This device has been located by the processing element responsible for system configuration.

'b0 - The device has not been previously discovered

'b1 - The device has been discovered by another processing element

1'b0
RSRV [28:0] RO Reserved 29'b0
Table 62.  Port 0 Local AckID CSR—Offset: 0x148
Field Bits Access Function Default
RSRV [31:29] RO Reserved 3'b0
INBOUND_ACKID [28:24] RO Next expected packet ackID. 5’b0
RSRV [23:13] RO Reserved 11’b0
OUTSTANDING_
ACKID [12:8] RO Next expected acknowledge control-symbol ackID. 5'b0
RSRV [7:5] RO Reserved 3'b0
OUTBOUND_ACKID [4:0] RO Next transmitted packet ackID. 5'b0
Table 63.  Port 0 Error and Status CSR—Offset: 0x158
Field45 Bits Access Function Default
RSRV [31:21] RO Reserved 11'b0
OUT_RTY_ENC [20] RW1C Output port has encountered a retry condition. In all cases, this condition is caused by the port receiving a packet-retry control symbol. This bit is set if the OUT_RTY_STOP bit is set. 1'b0
OUT_RETRIED [19] RO Output port has received a packet-retry control symbol and cannot make forward progress. This bit is cleared when a packet-accepted or packet-not-accepted control symbol is received. 1'b0
OUT_RTY_STOP [18] RO Output port has been stopped due to a retry and is trying to recover. When a port receives a packet_retry control symbol, it enters the Output Retry Stopped state. In this state, the port transmits a restart-from-retry control symbol to its link partner. The link partner exits the Input Retry Stopped state and normal operation resumes. The port exits the Output Retry Stopped state. 1'b0
OUT_ERR_ENC [17] RW1C Output port has encountered a transmission error and has possibly recovered from it. This bit is set when the OUT_ERR_STOP bit is set. 1'b0
OUT_ERR_STOP [16] RO Output port has been stopped due to a transmission error and is trying to recover. The output port is in the Output Error Stopped state. The port enters into this state when it receives a packet-not-accepted control symbol. To exit from this state, the port issues an input-status link-request/input-status (restart-from-error) control symbol. The port waits for the link-response control symbol and exits the Output Error Stopped state. 1'b0
RSRV [15:11] RO Reserved 5'b0
IN_RTY_STOP [10] RO Input port is stopped due to a retry. When the receiver issues a packet-retry control symbol to its link partner, it enters the Input Retry Stopped state. The receiver issues a packet-retry when sufficient buffer space is not available to accept the packet for that specific priority. The receiver continues in the Input Retry Stopped state until it receives a restart-from-retry control symbol. 1'b0
IN_ERR_ENC [9] RW1C Input port has encountered a transmission error. This bit is set if the IN_ERR_STOP bit is set. 1'b0
IN_ERR_STOP [8] RO Input port is stopped due to a transmission error. The port is in the Input Error Stop state.

The following conditions cause the input port to transition to this state:

  • Cancellation of a packet by using the restart-from-retry control symbol.
  • Invalid character or valid character other than A, K, or R in an idle sequence.
  • Single bit transmission errors.
  • Any of the following link protocol violations:


    Unexpected packet accepted

    Unexpected packet-retry

    Unexpected packet-not-accepted packet Acknowledgment control symbol with an unexpected packet_ackID

    Link time-out while waiting for an acknowledgment control symbol


  • Corrupted control symbols, that is, CRC violations on the symbol.
  • Any of the following Packet Errors:


    Unexpected ackID value

    Incorrect CRC value

    Invalid characters or valid nondata characters

    Max data payload violations


    The recovery mechanism consists of these steps:

    Issue a packet-not-accepted control symbol.

    Wait for link-request/input-status control symbol.

    Send link-response control symbol.

1'b0
RSRV [7:5] RO Reserved 3'h0
PWRITE_PEND [4] RO This register is not implemented and is reserved. It is always set to zero. 1'b0
RSRV [3] RO Reserved 1'b0
PORT_ERR [2] RW1C This bit is set if the input port error recovery state machine encounters an unrecoverable error or the output port error recovery state machine enters the fatal_error state.

The input port error recovery state machine encounters an unrecoverable error if it times out while waiting for a link-request after sending a packet-not-accepted control symbol.

The output port error recovery state machine enters the fatal_error state if the following sequence of events occurs:

The output port error recovery state machine enters the stop_output state when it receives a packet-not-accepted control symbol. In response, it sends the input-status link-request/input-status (restart-from-error) control symbol.

One of the following events occurs in response to the link-request control symbol:

If the link-response is received but the ackID is outside of the outstanding ackID set, or the port_status value is Error, then the output port error recovery state machine enters the fatal_error state.

If the port times out before receiving link-response, and the number of times this time-out event has occurred reaches the number you set in the RapidIO parameter editor as the value for Link-request attempts, then the output port error recovery state machine enters the fatal_error state.

When the PORT_ERR bit is set, the RapidIO IP core performs an internal soft reset sequence, as described in “Fatal Errors”.

The port_error output signal mirrors this register bit.

1'b0
PORT_OK [1] RO Input and output ports are initialized and can communicate with the adjacent device. This bit is asserted when port_initialized is asserted and the following conditions exist:
  • The IP core has received at least 7 status control symbols.
  • The output port retry recovery state machine is not in the stop_output state.
  • The output port error recovery state machine is not in the stop_output state.
  • The input port retry recovery state machine is not in the stop_input state.
  • The input port error recovery state machine is not in the stop_input state.
1'b0
PORT_UNINIT [0] RO Input and output ports are not initialized and are in training mode. This bit is the negation of the PORT_OK bit. 1'b1
Table 64.  Port 0 Control CSR—Offset: 0x15C
Field Bits Access Function Default
PORT_WIDTH [31:30] RO Hardware width of the port:

'b00—Single-lane port.

'b10—Two-lane port.

'b01—Four-lane port.

''b11—Reserved.

 2'b00 (for 1x variations),

2'b10 (for 2x variations),

2'b01 (for 4x variations)46

INIT_WIDTH [29:27] RO Width of the ports after being initialized:

'b000—Single lane port, lane 0.

'b001—Single lane port, redundancy lane (lane 1 for 2x variations and lane 2 for 4x variations).

'b010—Four-lane port.

'b011—Two-lane port.

‘b100 – 'b111—Reserved.

 3'b000 (for 1x variations),

3'b011 (for 2x variations),

3'b010 (for 4x variations)

PWIDTH_OVRIDE [26:24] UR0 Soft port configuration to override the hardware size:

'b000—No override.

'b001—Reserved.

'b010—Force single lane, lane 0.

'b011—Force single lane, redundancy lane.

'b100–'b111—Reserved.

 3'b000
PORT_DIS [23] RW Port disable:

'b0—Port receivers/drivers are enabled.

'b1—Port receivers are disabled, causing the drivers to send out idles.

  • When this bit transitions from 1 to 0, the initialization state machines’ force_reinit signal is asserted. This assertion causes the port to enter the SILENT state and to attempt to reinitialize the link, as described in section 4.12 of Part 6: LP-Serial Physical Layer Specification of the RapidIO Interconnect Specification, Revision 2.1.
  • When reception is disabled, the input buffers are kept empty until this bit is cleared.
  • When PORT_DIS is asserted and the drivers are disabled, the transmit buffer are reset and kept empty until this bit is cleared, any previously stored packets are lost, and any attempt to write a packet to the atx Atlantic interface is ignored by the Physical layer. New packets are NOT stored for later transmission.
1'b0
OUT_PENA [22] RW Output port transmit enable:

'b0—Port is stopped and not enabled to issue any packets except to route or respond to I/O logical MAINTENANCE packets, depending upon the functionality of the processing element. Control symbols are not affected and are sent normally.

'b1—Port is enabled to issue packets.

1'b1
IN_PENA [21] RW Input port receive enable:

'b0—Port is stopped and only enabled to respond I/O Logical MAINTENANCE requests. Other requests return packet-not-accepted control symbols to force an error condition to be signaled by the sending device

'b1—Port is enabled to respond to any packet

1'b1
ERR_CHK_DIS [20] RW This bit controls all RapidIO transmission error checking:

'b0—Error checking and recovery is enabled

'b1—Error checking and recovery is disabled

Device behavior when error checking and recovery is disabled and an error condition occurs is undefined.

1'b0
Multicast-event
Participant [19] RW Send incoming Multicast-event control symbols to this port (multiple port devices only). 1'b0
RSRV [18] RO Reserved 1'b0
Enumeration Boundary [17] RO This feature is not supported. 1'b0
RSRV [16:12] RO Reserved 5'b0
Re-transmit Suppression Mask [11:4] RO This feature is not supported. 8’b0
RSRV [3:1] RO Reserved 3’b0
PORT_TYPE [0] RO This bit indicates the port type, parallel or serial.

'b0—Parallel port

'b1—Serial port

 1'b1
Related Information
45 Refer to Error Detection and Management for details
46 Reflects the choice made in the RapidIO parameter editor.
Level Two Title