F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MII or PCS-Only Interface for FGT Transceivers 2.6. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.7. MAC Flow Control Interface 2.8. Status Interface 2.9. Avalon® Memory-Mapped Reconfiguration Interfaces 2.10. Precision Time Protocol Interface
2.10. Precision Time Protocol Interface x
2.10.1. Time-of-Day Interface 2.10.2. TX 2-Step Timestamp Interface 2.10.3. TX 1-Step Timestamp Interface 2.10.4. RX Timestamp Interface 2.10.5. PTP Status Interface 2.10.6. PTP Tile Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
5.1. Precision Time Protocol x
5.1.1. Clocking PTP Timestamp Accuracy PTP Timestamp Accuracy in Basic Mode PTP Timestamp Accuracy in Advanced Mode
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

5.1.1. Clocking PTP Timestamp Accuracy

The IP core supports two timestamps accuracy modes, Basic and Advanced. In advanced mode, additional logic generates the high accuracy PTP timestamps.

PTP Timestamp Accuracy in Basic Mode

When you select Basic in the Timestamp accuracy mode under PTP tab in the parameter editor for F-Tile Ethernet Multirate IP core, TX and RX data paths of multiple Ethernet IP instances share a single TOD clock output.
  • The time-of-day (TOD) module can be shared across multiple IP instances of different data rates
  • Any 390.625 MHz frequency clock source can drive the TOD clock
Figure 10. TOD Clock and TOD Connections in Basic Accuracy ModeThe figure displays recommended TOD clock connection. The TOD clock source should be 390.625 MHz.

PTP Timestamp Accuracy in Advanced Mode

When you select Advanced in the Timestamp accuracy mode under PTP tab in the parameter editor, the IP core requires a single Master TOD module and dedicated TOD Synchronizer and TOD modules for both, TX and RX PTP instances.

Figure 11. TOD Clock and TOD Connections in Advanced Accuracy ModeThe figure displays recommended TOD clock connection.
In your design, you can share the TX TOD across multiple instances. Follow these conditions when sharing TX TOD:
  • TX transceiver reference clocks of each port are shared, or from the source with the same clock frequency PPM
  • TX transceiver channel that output the clock driving the shared TOD must not reset after the TX div clock is stable
  • While other ports are active, the IP does not allow dynamic reconfiguration to the port output that shared TX div clock. A dynamic reconfiguration of all ports together is allowed.
  • All ports operate at the same Ethernet rate
Figure 12. TOD Clock Connections in Advanced Accuracy Mode: Sharing TX TOD
If you need to dynamically reconfigure your design to support 10G Ethernet with PTP, Intel® recommends the following TOD connection for PTP in Advanced accuracy mode. Single instance of TOD Synchronizer can only support a single synchronization mode and TOD module is needed for each rate in TX and RX PTP data path of each port. You must correctly configure the TOD multiplexer according to the current operating state.
Figure 13. TOD Clock Connections in Advanced Accuracy Mode for 10G Dynamic Reconfiguration
In your design, you can share TX TOD across multiple instances. Follow these conditions when sharing TX TOD:
  • TX transceiver reference clocks of each port are shared, or from the source with the same clock frequency PPM
  • TX transceiver channel that output the clock driving the shared TOD must not reset after the TX div clock is stable
  • While other ports are active, the IP does not allow dynamic reconfiguration to the port output that shared TX div clock. A dynamic reconfiguration of all ports together is allowed.
  • All ports operate at the same Ethernet rate
Figure 14. TOD Clock Connections in Advanced Accuracy Mode for 10G Dynamic Reconfiguration:Sharing TX TOD
The table below specifies the timestamp accuracy modes support per profile within each reconfiguration group. If you plan to use a secondary profile that does not support advanced accuracy mode, you must set the timestamp accuracy to Basic.
Table 47.  Supported Timestamp Accuracy Modes per Profile
Reconfiguration Group Base and Supported Secondary Profiles Supported Timestamp Accuracy Mode
25GE-1 Reconfigurable 1x 25GE-1 Basic, Advanced
1x 10GE-1 Basic, Advanced
50GE-1 Reconfigurable 1x 50GE-1 Basic, Advanced
1x 25GE-1 Basic, Advanced
1x 10GE -1 Basic, Advanced
100GE-4 Reconfigurable 1x 100GE-4 Basic, Advanced
2x 50GE-2 Basic, Advanced
1x 100GE-2 Basic, Advanced
4x 25GE-1 Basic, Advanced
4x 10GE-1 Basic, Advanced
2x 50GE-1 Basic
100GE-2 Reconfigurable 1x 100GE-2 Basic, Advanced
2x 50GE-1 Basic, Advanced
2x 25GE-1 Basic, Advanced
2x 10GE-1 Basic, Advanced
1x 50GE-2 Basic
400GE-8 Reconfigurable 1x 400GE-8 Basic, Advanced
2x 200GE-4 Basic, Advanced
4x 100GE-2 Basic, Advanced
200GE-4 Reconfigurable 1x 200GE-4 Basic, Advanced
2x 100GE-2 Basic, Advanced
1x 100GE-4 Basic
2x 50GE-2 Basic
4x 50GE-1 Basic, Advanced
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