Visible to Intel only — GUID: snh1647372114511
Ixiasoft
2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MII or PCS-Only Interface for FGT Transceivers
2.6. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.7. MAC Flow Control Interface
2.8. Status Interface
2.9. Avalon® Memory-Mapped Reconfiguration Interfaces
2.10. Precision Time Protocol Interface
Visible to Intel only — GUID: snh1647372114511
Ixiasoft
1.8.7. Transceiver Lane Mapping
The transceiver lane mapping defines a predictable mapping to the EMIBs or demaping from the EMIBs. Transceiver lane mappings specifies transceiver lane assignments for each supported profile within a reconfiguration group.
The below restriction tables specify the maximum number of ports and the maximum number of transceiver lanes defined for each reconfiguration group.
Transceiver Lane / Number of ports |
FGT1 | FGT0 |
---|---|---|
1 port using 2 lanes | Port 0, Lane 0 | Port 0, Lane 1 |
2 ports using 1 lane each | Port 0, Lane 0 | Port 1, Lane 0 |
Transceiver Lane / Number of ports |
FGT3 | FGT2 | FGT1 | FGT0 |
---|---|---|---|---|
1 port using 4 lanes | Port 0, Lane 0 | Port 0, Lane 1 | Port 0, Lane 2 | Port 0, Lane 3 |
1 port using 2 lanes | Port 0, Lane 0 | Port 0, Lane 1 | Unused | Unused |
1 port using 1 lane | Port 0, Lane 0 | Unused | Unused | Unused |
2 ports using 2 lanes each | Port 0, Lane 0 | Port 0, Lane 1 | Port 2, Lane 0 | Port 2, Lane 1 |
2 ports using 1 lane each | Port 0, Lane 0 | Port 2, Lane 0 | Unused | Unused |
4 ports using 1 lane each | Port 0, Lane 0 | Port 1, Lane 0 | Port 2, Lane 0 | Port 3, Lane 0 |
Transceiver Lane / Number of ports |
FGT7 | FGT6 | FGT5 | FGT4 | FGT3 | FGT2 | FGT1 | FGT0 |
---|---|---|---|---|---|---|---|---|
1 port using 8 lanes | Port 0, Lane 0 | Port 0, Lane 1 | Port 0, Lane 2 | Port 0, Lane 3 | Port 0, Lane 4 | Port 0, Lane 5 | Port 0, Lane 6 | Port 0, Lane 7 |
2 ports using 4x lanes each | Port 0, Lane 0 | Port 0, Lane 1 | Port 0, Lane 2 | Port 0, Lane 3 | Port 2, Lane 0 | Port 2, Lane 1 | Port 2, Lane 2 | Port 2, Lane 3 |
4 ports using 2x lanes each | Port 0, Lane 0 | Port 0, Lane 1 | Port 1, Lane 0 | Port 1, Lane 1 | Port 2, Lane 0 | Port 2, Lane 1 | Port 3, Lane 0 | Port 3, Lane 1 |