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2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MII or PCS-Only Interface for FGT Transceivers
2.6. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.7. MAC Flow Control Interface
2.8. Status Interface
2.9. Avalon® Memory-Mapped Reconfiguration Interfaces
2.10. Precision Time Protocol Interface
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2.10.6. PTP Tile Interface
A 1-bit ptp_link signal is available per each F-tile Ethernet Multirate IP core. When PTP is enabled, you must connect the PTP link port of one or more Ethernet Multirate IP to the PTP Tile Adapter. The Support Logic Generation step in the Intel® Quartus® Prime software automatically generates the actual PTP signals between the F-Tile Ethernet Multirate IP core's PTP soft logic and the PTP tile adapter.
The table displays the interface details for different numbers of ports.
Maximum Number of Ports | Signal Name |
---|---|
1, 2, or 4 | ptp_link |