Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 5/27/2022
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Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines x
Intel® MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices Document Revision History for Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins Intel® MAX® 10 (Single Supply) FPGA Intel® MAX® 10 (Dual Supply) FPGA Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices x
Example 1— Intel® MAX® 10 (Dual Supply) FPGA Example 2— Intel® MAX® 10 (Dual Supply) FPGA Example 3— Intel® MAX® 10 (Dual Supply) FPGA Example 4— Intel® MAX® 10 (Single Supply) FPGA Example 5— Intel® MAX® 10 (Single Supply) FPGA Example 6— Intel® MAX® 10 (Single Supply) FPGA
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

Configuration/JTAG Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 2.  Configuration/JTAG Pins
Pin Name Pin Functions Pin Description Connection Guidelines
CONFIG_SEL Input, I/O

This is a dual-purpose pin. Use this pin to choose the configuration image in the dual-configuration images mode.

If the CONFIG_SEL pin is set to low, the first configuration image is configuration image 0. If the CONFIG_SEL pin is set to high, the first configuration image is configuration image 1.

This pin is read before user mode and before the nSTATUS pin is asserted.

To select the configuration image in the dual-configuration images mode, connect a weak 10-KΩ pull-up or weak 10-KΩ pull-down to this pin externally during the power-up phase.

By default this pin is tri-stated.

A weak 10-KΩ pull-up or weak 10-KΩ pull-down is not needed if you do not plan to use the dual configuration images mode.

See Note 10.
CONF_DONE Bidirectional (open-drain), I/O

This is a dual-purpose pin. The CONF_DONE pin drives low before and during configuration. After all configuration data is received without error and the initialization cycle starts, the CONF_DONE pin is released.

The CONF_DONE pin should be pulled high to VCCIO Bank 8 by an external 10-KΩ pull-up resistor.

The Intel® MAX® 10 device will not enter the initialization and user mode if the CONF_DONE pin is pulled low.

Hot socketing is disabled for the CONF_DONE pin. Due to this, a glitch maybe observed at the CONF_DONE pin. To monitor the status of the pin, Intel recommends to implement input buffer with hysteresis and digital filtering with the sampling duration larger than 5.5 ms in the external device to avoid false trip.

CRC_ERROR Output (open-drain), I/O

This is a dual-purpose pin. Active high signal indicates that the error detection circuitry has detected errors in the configuration CRAM bits.

The CRC_ERROR pin is an optional pin and is used when the cyclic redundancy check (CRC) error detection circuitry is enabled.

Intel recommends you to tie the CRC_ERROR pin to VCCIO, GND, or leave the pin unconnected when the CRC error detection circuitry is disabled or when you are not using the CRC_ERROR pin.

DEV_CLRn Input, I/O

This is a dual-purpose pin. Optional chip-wide reset pin that allows you to override all clears on all device registers.

When this pin is driven low, all registers are cleared. When this pin is driven high, all registers behave as programmed.

The DEV_CLRn pin does not affect JTAG boundary-scan or programming operations. You can enable this pin by turning on the Enable device-wide reset (DEV_CLRn) option in the Intel® Quartus® Prime software.

Intel recommends you to tie the DEV_CLRn pin to GND when the Enable device-wide reset (DEV_CLRn) option is disabled and not used as a user I/O pin. You can also tie the DEV_CLRn pin to VCCIO or leave the DEV_CLRn pin unconnected provided that the Enable device-wide reset (DEV_CLRn) option is disabled and not used as a user I/O pin. When you leave the DEV_CLRn pin unconnected, Intel recommends you to set the DEV_CLRn pin to input tri-state with a weak pull-up.
DEV_OE Input, I/O

This is a dual-purpose pin. Optional pin that allows you to override all tri-states on the device.

When this pin is driven low, all I/O pins are tri-stated. When this pin is driven high, all I/O pins behave as programmed.

You can enable this pin by turning on the Enable device-wide output enable (DEV_OE) option in the Intel® Quartus® Prime software.

Intel recommends you to tie the DEV_OE pin to GND when the Enable device-wide output enable (DEV_OE) option is disabled and not used as a user I/O pin. You can also tie the DEV_OE pin to VCCIO or leave the DEV_OE pin unconnected provided that the Enable device-wide output enable (DEV_OE) option is disabled and not used as a user I/O pin. When you leave the DEV_OE pin unconnected, Intel recommends you to set the DEV_OE pin to input tri-state with a weak pull-up.

JTAGEN I/O

This is a dual-purpose pin. This pin functions according to the setting of the JTAG pin sharing option bit.

If the JTAG pin sharing is not enabled, the JTAGEN pin is a regular I/O pin and JTAG pins function as JTAG dedicated pins.

If the JTAG pin sharing is enabled and the JTAGEN pin is pulled low, JTAG pins function as dual-purpose pins.

If the JTAG pin sharing is enabled and the JTAGEN pin is pulled high, JTAG pins function as JTAG dedicated pins.

This pin has an internal 25-kΩ pull up.

In user mode, to use JTAG pins as regular I/O pins, tie the JTAGEN pin to a weak 1-kΩ pull-down. To use JTAG pin as dedicated pin, tie the JTAGEN pin to a weak 10-kΩ pull-up.

nCONFIG Input, I/O

This is a dual-purpose pin, as an nCONFIG pin or a single-ended input pin in user mode. Before user mode, these pins function as configuration pins.

During configuration mode, the pin name is nCONFIG. During user mode, the pin name is Input_only.

If you pull this pin low during user mode the device will lose its configuration data, enter a reset state, and tri-state all I/O pins. Pulling this pin to a logic-high level initiates reconfiguration.

Upon power up, the nCONFIG pin must be pulled high. Connect this pin directly or through a 10-kΩ resistor to VCCIO.

nSTATUS Bidirectional (open-drain), I/O

This is a dual-purpose pin, as an nSTATUS pin or a regular user I/O pin in user mode. By default, the nSTATUS pin is a dedicated configuration pin in user mode.

The device drives the nSTATUS pin low immediately after power up and releases the pin after power-on reset (POR) time.

As a status output, the nSTATUS pin is pulled low if an error occurs during configuration.

As a status input, the device enters an error state when the nSTATUS pin is driven low by an external source during configuration or initialization.

Pull the nSTATUS pin high using an external 10-kΩ pull-up resistor.Pull the nSTATUS pin high using an external 10-kΩ pull-up resistor.

Hot socketing is disabled for the nSTATUS pin. Due to this, a glitch maybe observed at the nSTATUS pin. To monitor the status of the pin, Intel recommends to implement input buffer with hysteresis and digital filtering with the sampling duration larger than 5.5 ms in the external device to avoid false trip.

TCK Input, I/O

JTAG test clock input pin. This is a dual-purpose pin.

This TCK pin does not support internal weak pull-down. Connect this pin to an external 1-KΩ – 10-KΩ pull-down resistor.

By default this pin is tri-stated.

If the configuration voltage exceed 2.5 V (VCCIO Bank 1B), Intel recommends you to add an external capacitor and diode to reduce voltage overshoot.

For more information about overshoot prevention circuitry, refer to the Intel® MAX® 10 Configuration User Guide.

TDO Output, I/O

This is a dual-purpose pin, as a JTAG TDO pin or a regular user I/O pin in user mode.

Intel recommends you to leave this pin unconnected if not used.

By default this pin is tri-stated.

If the configuration voltage exceed 2.5 V (VCCIO Bank 1B), Intel recommends you to add an external capacitor and diode to reduce voltage overshoot.

For more information about overshoot prevention circuitry, refer to the Intel® MAX® 10 Configuration User Guide.

TDI Input, I/O

This is a dual-purpose pin, as a JTAG TDI pin or a regular user I/O pin in user mode.

You can disable the JTAG circuitry by connecting the TDI pin to VCCIO Bank 1B.

This pin has a weak internal pull-up. For configuration voltage of 2.5 V, 3.0 V, or 3.3 V, connect this pin through a 10-kΩ resistor to 2.5 V (VCCIO Bank 1B) to prevent voltage overshoot. If power supplies exceed 2.5 V, Intel recommends you to add an external capacitor and diode to reduce voltage overshoot. For configuration voltage of 1.5 V and 1.8 V, connect this pin through a 10-kΩ resistor to 1.5 V or 1.8 V (VCCIO Bank 1B) supply, respectively.

For more information about overshoot prevention circuitry, refer to the Intel® MAX® 10 Configuration User Guide.

TMS Input, I/O

This is a dual-purpose pin, as a JTAG TMS pin or a regular user I/O pin in user mode.

You can disable the JTAG circuitry by connecting the TMS pin to VCCIO Bank 1B.

This pin has a weak internal pull-up. For configuration voltage of 2.5 V, 3.0 V, or 3.3 V, connect this pin through a 10-kΩ resistor to 2.5 V (VCCIO Bank 1B) to prevent voltage overshoot. If power supplies exceed 2.5 V, Intel recommends you to add an external capacitor and diode to reduce voltage overshoot. For configuration voltage of 1.5 V and 1.8 V, connect this pin through a 10-kΩ resistor to 1.5 V or 1.8 V (VCCIO Bank 1B) supply, respectively.

For more information about overshoot prevention circuitry, refer to the Intel® MAX® 10 Configuration User Guide.

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