Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 5/27/2022
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Document Table of Contents x
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines x
Intel® MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices Document Revision History for Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins Intel® MAX® 10 (Single Supply) FPGA Intel® MAX® 10 (Dual Supply) FPGA Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices x
Example 1— Intel® MAX® 10 (Dual Supply) FPGA Example 2— Intel® MAX® 10 (Dual Supply) FPGA Example 3— Intel® MAX® 10 (Dual Supply) FPGA Example 4— Intel® MAX® 10 (Single Supply) FPGA Example 5— Intel® MAX® 10 (Single Supply) FPGA Example 6— Intel® MAX® 10 (Single Supply) FPGA
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

External Memory Interface Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 4.  External Memory Interface Pins
Pin Name Pin Functions Pin Description Connection Guidelines
DQ[#]R I/O, DQ Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, use with caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQS[#]R I/O, DQS Optional data strobe signal for use in external memory interfacing. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQSn[#]R I/O, DQSn Optional complementary data strobe signal for use in external memory interfacing. Connect unused pins as defined in the Intel® Quartus® Prime software.
DM[#]R I/O, DM A low signal on the DM pin indicates that the write is valid. Driving the DM pin high results in the memory masking of the DQ signals. Connect unused pins as defined in the Intel® Quartus® Prime software.
CK_[6] I/O, Output Input clock for external memory devices. Connect unused pins as defined in the Intel® Quartus® Prime software.
CK#_[6] I/O, Output Input clock for external memory devices, inverted CK. Connect unused pins as defined in the Intel® Quartus® Prime software.
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