Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 5/27/2022
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Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines x
Intel® MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices Document Revision History for Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins Intel® MAX® 10 (Single Supply) FPGA Intel® MAX® 10 (Dual Supply) FPGA Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices x
Example 1— Intel® MAX® 10 (Dual Supply) FPGA Example 2— Intel® MAX® 10 (Dual Supply) FPGA Example 3— Intel® MAX® 10 (Dual Supply) FPGA Example 4— Intel® MAX® 10 (Single Supply) FPGA Example 5— Intel® MAX® 10 (Single Supply) FPGA Example 6— Intel® MAX® 10 (Single Supply) FPGA
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

Differential I/O Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 3.  Differential I/O Pins
Pin Name Pin Functions Pin Description Connection Guidelines
DIFFIO_RX_L[#:#][n,p], DIFFOUT_L[#:#][n,p] I/O, dedicated RX channel, emulated LVDS output channel

When used as differential inputs, these are true LVDS receiver channels on left I/O banks. Pins with a “p” suffix carry the positive signal for the differential channel. Pins with an “n” suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

When used as differential outputs, these are emulated LVDS output channels on left I/O banks. External resistor network is needed for emulated LVDS output buffers. Pins with a “p” suffix carry the positive signal for the differential channel. Pins with an “n” suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

Connect unused pins as defined in the Intel® Quartus® Prime software.

For the number of LVDS pair count for each Intel® MAX® 10 device, refer to the respective device pinout file.

DIFFIO_RX_R[#:#][n,p], DIFFOUT_R[#:#][n,p] I/O, dedicated RX channel, emulated LVDS output channel

When used as differential inputs, these are true LVDS receiver channels on right I/O banks. Pins with a “p” suffix carry the positive signal for the differential channel. Pins with an “n” suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

When used as differential outputs, these are emulated LVDS output channels on right I/O banks. External resistor network is needed for emulated LVDS output buffers. Pins with a “p” suffix carry the positive signal for the differential channel. Pins with an “n” suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

Connect unused pins as defined in the Intel® Quartus® Prime software.

For the number of LVDS pair count for each Intel® MAX® 10 device, refer to the respective device pinout file.

DIFFIO_RX_T[#:#][n,p], DIFFOUT_T[#:#][n,p] I/O, dedicated RX channel, emulated LVDS output channel

When used as differential inputs, these are true LVDS receiver channels on top I/O banks. Pins with a “p” suffix carry the positive signal for the differential channel. Pins with an “n” suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

When used as differential outputs, these are emulated LVDS output channels on top I/O banks. External resistor network is needed for emulated LVDS output buffers. Pins with a “p” suffix carry the positive signal for the differential channel. Pins with an “n” suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

Connect unused pins as defined in the Intel® Quartus® Prime software.

For the number of LVDS pair count for each Intel® MAX® 10 device, refer to the respective device pinout file.

DIFFIO_RX_B[#:#][n,p], DIFFOUT_B[#:#][n,p] I/O, dedicated RX channel, emulated LVDS output channel

When used as differential inputs, these are true LVDS receiver channels on bottom I/O banks. Pins with a “p” suffix carry the positive signal for the differential channel. Pins with an “n” suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

When used as differential outputs, these are emulated LVDS output channels on bottom I/O banks. External resistor network is needed for emulated LVDS output buffers. Pins with a “p” suffix carry the positive signal for the differential channel. Pins with an “n” suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

Connect unused pins as defined in the Intel® Quartus® Prime software.

For the number of LVDS pair count for each Intel® MAX® 10 device, refer to the respective device pinout file.

DIFFIO_TX_RX_B[#:#][n,p] I/O, dedicated TX/RX channel These are true LVDS transmitter channels or true LVDS receiver channels on bottom I/O banks. Pins with a “p” suffix carry the positive signal for the differential channel. Pins with an “n” suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

Connect unused pins as defined in the Intel® Quartus® Prime software.

For the number of LVDS pair count for each Intel® MAX® 10 device, refer to the respective device pinout file.

High_Speed I/O

These are I/O pins. High_Speed I/O pins have higher performance compared to Low_Speed I/O pins.

High_Speed I/O pins reside in Banks 2, 3, 4, 5, 6, and 7.

 Connect unused pins as defined in the Intel® Quartus® Prime software.
Low_Speed I/O

These are I/O pins. Low_Speed I/O pins have lower performance compared to High_Speed I/O pins.

Low_Speed I/O pins reside in Banks 1A, 1B, and 8.

 Connect unused pins as defined in the Intel® Quartus® Prime software.
RDN I/O, Input

This pin is required for each OCT RS calibration block. OCT is only applicable for right I/O banks (banks 5 and 6) of 10M16, 10M25, and 10M50 devices.

This pin is a dual-purpose pin, you can use the RDN pin as a regular I/O pin if the OCT calibration is not used. When you use OCT calibration, connect the RDN pin to GND through an external resistor.

When you use OCT, tie these pins to GND through either a 25-, 34-, 40-, 48-, or 50-Ω resistor depending on the desired I/O standard. When the device does not use this dedicated input pin for the external precision resistor or as an I/O pin, Intel recommends you to connect the RDN pin to GND.
RUP I/O, Input

This pin is required for each OCT RS calibration block. OCT is only applicable for right I/O banks (banks 5 and 6) of 10M16, 10M25, and 10M50 devices.

This pin is a dual-purpose pin, you can use the RUP pin as a regular I/O pin if the OCT calibration is not used. When you use OCT calibration, connect the RUP pin to VCCN through an external resistor.

When you use OCT, tie these pins to the required VCCIO banks through either a 25-, 34-, 40-, 48-, or 50-Ω resistor depending on the desired I/O standard. When the device does not use this dedicated input pin for the external precision resistor or as an I/O pin, Intel recommends you to connect the RUP pin to VCCIO of the bank in which the RUP pin resides or GND.
VREFB<#>N0 Power, I/O

These pins are dual-purpose pins. For Banks 1A and 1B, VREF pins are shared.

Input reference voltage for each I/O bank. If a bank uses a voltage referenced I/O standard for input operation, then these pins are used as the voltage-reference pins for the bank.

If you are not using the VREF pins in banks or shared banks, connect unused pins as defined in the Intel® Quartus® Prime software.

When VREF pins are used as I/O pins, they have higher capacitance than regular I/O pins which will slow the edge rates and affect I/O timing.

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