Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 5/27/2022
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Document Table of Contents x
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines x
Intel® MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices Document Revision History for Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins Intel® MAX® 10 (Single Supply) FPGA Intel® MAX® 10 (Dual Supply) FPGA Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices x
Example 1— Intel® MAX® 10 (Dual Supply) FPGA Example 2— Intel® MAX® 10 (Dual Supply) FPGA Example 3— Intel® MAX® 10 (Dual Supply) FPGA Example 4— Intel® MAX® 10 (Single Supply) FPGA Example 5— Intel® MAX® 10 (Single Supply) FPGA Example 6— Intel® MAX® 10 (Single Supply) FPGA
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

Intel® MAX® 10 (Dual Supply) FPGA

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 8.   Intel® MAX® 10 (Dual Supply) FPGA
Pin Name Pin Functions Pin Description Connection Guidelines
VCC Power Power supply pin for core and periphery.

Connect all VCC pins to 1.2-V power supply.

Decoupling of these pins depends on the design decoupling requirements of the specific board. See Note 4.

VCCIO[#] Power

I/O supply voltage pins for banks 1 through 8. Each bank supports different voltage level.

The VCCIO pin supplies power to the input and output buffers for all I/O standards.

The VCCIO pin powers up the JTAG and configuration pins.

Connect these pins to 1.0-, 1.2-, 1.35-, 1.5-, 1.8-, 2.5-, 3.0-, or 3.3-V power supplies, depending on the I/O standard assigned to each I/O bank.

Note: The 1.0-V VCCIO is not supported on I/O banks 1B and 8. For dual-supply device option, the 1.0-V VCCIO is only supported on specific Intel® MAX® 10 devices. For the list of supported devices, refer to the Supported I/O Standards section in the Intel® MAX® 10 General Purpose I/O User Guide.

If you power-up a device from the power-down state, you need to power the VCCIO for bank 1B (bank 1 for 10M02 devices), bank 8, and the core to the appropriate level for the device to exit POR. The Intel® MAX® 10 device enters the configuration stage after exiting the power-up stage with a small POR delay. The VCCIO for bank 1B (bank 1 for 10M02 devices) and bank 8 must be powered up to a voltage between 1.5V – 3.3V during configuration.

If you are migrating from other Intel® MAX® 10 devices to the 10M02 device, the VCCIO1A and VCCIO1B pins are shorted to the VCCIO1 pin of the 10M02 device.

If you do not enable the ADC feature, you may connect VCCIO1A and VCCIO1B pins to different voltage levels, provided that the VREF pin is not used. If the VREF pin is used, you must connect the VCCIO1A and VCCIO1B pins to the same voltage level.

If you enable the ADC feature, connect VCCIO1A and VCCIO1B to 2.5 V.

The power supply sharing between VCCIO1A and VCCIO1B pins requires filtering to isolate the noise. The filter should be located near to VCCIO1A pins. Only 10M02 devices do not require filtering if VCCIO1A and VCCIO1B share the same power supply. When the ADC feature is enabled, filter is required.

If you are migrating from the 10M08 or 10M16 device to the 10M02 device with ADC enabled, replace the filter with 0-Ω resistor in the 10M02 device.

For details about the available VCCIO pins for each Intel® MAX® 10 device, refer to the respective device pinout file.

Decoupling of these pins depends on the design decoupling requirements of the specific board. See Note 4.
VCCA[1..4] Power Power supply pins for PLL analog block.

Connect these pins to a 2.5 V power supply even if the PLL is not used. These pins must be powered up and powered down at the same time. Connect all VCCA pins together.

VCCA power supply to the FPGA should be isolated for better jitter performance. See Notes 5 and 6.

For more information about the UFM and CFM power-down requirement, refer to the Intel® MAX® 10 User Flash Memory User Guide.

VCCD_PLL[1..4] Power Power supply pins for PLL digital block.

Connect VCCD_PLL[1..4] pins to 1.2 V power supply even if the PLL is not used.

Connect all VCCD_PLL[1..4] pins together.

Intel recommends you to keep these pins isolated from other VCC pins for better jitter performance. See Notes 5 and 7.

VCCA_ADC Power Power supply pin for ADC analog block.

Connect the VCCA_ADC pin to the recommended power supply specification for the best ADC performance.

Tie the VCCA_ADC pin to any 2.5 V power domain if you are not using ADC, and do not tie the VCCA_ADC pin to GND.

Decoupling of these pins depends on the design decoupling requirements of the specific board. See Note 4.

VCCINT Power Power supply pin for ADC digital block.

Connect the VCCINT pin to the recommended power supply specification for the best ADC performance.

Tie the VCCINT pin to any 1.2 V power domain if you are not using ADC.

Decoupling of these pins depends on the design decoupling requirements of the specific board. See Note 4.

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