Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

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ID 683232
Date 5/27/2022
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Document Table of Contents x
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines x
Intel® MAX® 10 FPGA Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices Document Revision History for Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines
Intel® MAX® 10 FPGA Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins External Memory Interface Pins Reference Pins Analog Input Pins Intel® MAX® 10 (Single Supply) FPGA Intel® MAX® 10 (Dual Supply) FPGA Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® MAX® 10 FPGA Devices x
Example 1— Intel® MAX® 10 (Dual Supply) FPGA Example 2— Intel® MAX® 10 (Dual Supply) FPGA Example 3— Intel® MAX® 10 (Dual Supply) FPGA Example 4— Intel® MAX® 10 (Single Supply) FPGA Example 5— Intel® MAX® 10 (Single Supply) FPGA Example 6— Intel® MAX® 10 (Single Supply) FPGA
Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

Example 5— Intel® MAX® 10 (Single Supply) FPGA

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 14.  Power Supply Sharing Guidelines for Intel® MAX® 10 (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 3.0V/3.3V (E144, M153, U169, and U324 Packages)Example Requiring 2 Power Regulator
Power Pin Name Regulator Count Voltage Level (V) Supply Tolerance Power Source Regulator Sharing Notes
VCC_ONE 1 3.0/3.3 ± 5% Switcher (*) Share Both VCCA and VCC_ONE must share a single power source using proper isolation filter.
VCCA Isolate
VCCIO1B 2 3.0/3.3 ± 5% Switcher (*) Share You have the option to share VCCIO1B and VCCIO[2..8] when these pins are powered up at 3.0V/3.3V.
VCCIO[2..8]
VCCIO1A Isolate You have the option to share VCCIO1A with VCCIO1B and VCCIO[2..8] using proper isolation filter.

(*)When using a switcher to supply these voltages, the switcher must be a low noise switcher as defined in note 9 of the Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines.

Notes:

  1. Use the EPE (Early Power Estimation) tool to assist in determining the power required for your specific design.
  2. Each board design requires its own power analysis to determine the required power regulators needed to satisfy the specific board design requirements. An example block diagram using the Intel® MAX® 10 FPGA device is provided in Figure 5.
  3. Refer to the Intel® MAX® 10 FPGA Configuration User Guide for maximum ramp rate requirement.
Figure 5. Example Power Supply Sharing Guidelines for Intel® MAX® 10 (Single Supply) FPGA – Using the ADC Feature and VCCIO[2..8] Pins are Powered Up 3.0V/3.3V (E144, M153, U169, and U324 Packages)
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