AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.4.4.4. 1588 ToD Clock Registers

The following table shows the list of names, offsets and description for all the registers available in the Altera Ethernet IEEE 1588 ToD Clock module.

Note: Altera recommends maintain the register settings for this module as set in the reference design for optimum operation.
Table 11.   Register Description and Address Offset for 1588 TOD Clock
Byte Offset R/W Name Description HW Reset
0x0000 RW SecondsH
  • Bits 0 to 15: High-order 16-bit second field
  • Bits 16 to 31: Not used.
0x0
0x0004 RW SecondsL Bits 0 to 32: Low-order 32-bit second field. 0x0
0x0008 RW NanoSec Bits 0 to 32: 32-bit nanosecond field. 0x0
0x0010 RW Period
  • Bits 0 to 15: Period in fractional nanosecond
  • Bits 16 to 19: Period in nanosecond
  • Bits 20 to 31: Not used.
N
0x0014 RW AdjustPeriod The period for the offset adjustment.
  • Bits 0 to 15: Period in fractional nanosecond
  • Bits 16 to 19: Period in nanosecond
  • Bits 20 to 31: Not used.
0x0
0x0018 RW AdjustCount
  • Bits 0 to 19: The number of AdjustPeriod clock cycles used during offset adjustment
  • Bits 20 to 31: Not used.
0x0
0x001C RW DriftAdjust The drift of ToD adjusted periodically by adding a correction value as configured in this register space.
  • Bits 0 to 15: Adjustment value in fractional nanosecond (DRIFT_ADJUST_FNS). This value is added into the current ToD during the adjustment.
  • Bits 16 to 19: Adjustment value in nanosecond (DRIFT_ADJUST_NS). This value is added into the current ToD during the adjustment.
  • Bits 20 to 32: Not used.
 0x0
0x0020 RW DriftAdjustRate The count of clock cycles for each ToD’s drift adjustment to take effect.
  • Bits 0 to 15: The number of clock cycles (ADJUST_RATE). The ToD adjustment happens once after every period in number of clock cycles as indicated by this register space.
  • Bits 20 to 32: Not used.
 0x0
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