AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.4.1.5. FIFO

A FIFO is used to associate a PTP event with a timestamp for later retrieval. For example, in a 2-step operation, the FIFO will be used to remember the time that a packet has gone out so that it can be looked up and retrieved at the time that the CPU is ready to send out the follow-up response. Though the 1588 protocol is a slow protocol with 128 frames per second, the 1588 packets may arrive in burst or many contexts such as simultaneous flows or many PTP domains can coexist in a single clock device. Hence, a FIFO is sometimes required depending on the system performance requirements in a 2-step operation. Similarly, in 1-step operation, the timestamp T3 and optionally T2 needs to be collected by the PTP stack through a FIFO. The use cases are an Ordinary Clock-Master in 2-step, Boundary Clock-Master in 2-step, Ordinary Clock-Slave in both 1-step and 2-step, Boundary Clock-Slave in both 1-step and 2-step & Transparent Clock (TC) in 2-step. A typical size of the FIFO required is a network parameter, which can approximately range from 64 to 256 entrees.

The FIFO stores the timestamp along with the signature of the packet for the CPU to read the timestamp later. The CPU can match the timestamp’s signature with its signature of the packet before accepting the timestamp. If the timestamp is read out of order, the CPU can keep a shadow copy of the entry to match with other signatures and read the FIFO for the packet in context. A FIFO works more efficiently than a CAM the timestamps are read in order.

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