AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.4.4.3. PTP Control Registers

The following table shows the list of names, offsets and description for all the registers available in the PTP Control module.
Note: Altera recommends maintain the register settings for this module as set in the reference design for optimum operation.
Table 10.  Register Description and Address Offset for PTP Control Module
Word Offset Bits Name Type Reset Value Description
0x00 1:0 txrx_pkt_parser_clock_mode RW 2'b00

Specify the operating clock mode for PTP port.

2'b00: Ordinary Clock

2'b01: Boundary Clock

2'b10: End-to-end Transparent Clock

2'b11: Peer-to-peer Transparent Clock
8 tx_pkt_parser_two_step_mode RW 1'b0

Specify the operation mode for the synchronization process.

1'b0: 1-step operation mode

1'b1: 2-step operation mode.
10 tx_pkt_parser_packet_with_crc RW 1'b0

Enable the packet parser to indicate whether the incoming packet to the MAC includes CRC.

This register is required by TX packet parser to calculate the offset location for checksum corrector for UDP/IPv6 packets.

0x04 0 rx_pkt_flt_fwd_user_ucast_match RW 1'b0

Forward unicast packet that matched the MAC address to user logic.

1'b0: Allow unicast packet which matched the MAC address to be forwarded to user logic.

1'b1: Drop unicast packet that matched the MAC address.

1 rx_pkt_flt_fwd_user_ucast_xmatch RW 1'b1

Forward unicast packet that does not matched the MAC address to user logic.

1'b0: Drop unicast packet that do not match the MAC address.

1'b1: Allow unicast packet which does not match the MAC address to be forwarded to user logic.

2 rx_pkt_flt_fwd_user_mcast RW 1'b1

Forward multicast packet to user logic.

1'b0: Drop multicast packet.

1'b1: Allow multicast packet to be forwarded to user logic.

3 rx_pkt_flt_fwd_user_bcast RW 1'b1

Forward Broadcast packet to user logic.

1'b0: Drop broadcast packet.

1'b1: Allow broadcast packet to be forwarded to user logic.

8 rx_pkt_flt_fwd_sw_ucast_match RW 1'b1 Forward unicast packet that matched the MAC address to software.
9 rx_pkt_flt_fwd_sw_ucast_xmatch RW 1'b0 Forward unicast packet that does not matched the MAC address to software.
10 rx_pkt_flt_fwd_sw_mcast RW 1'b1 Forward multicast packet to software.
11 rx_pkt_flt_fwd_sw_bcast RW 1'b1 Forward Broadcast packet to software.
0x05 31:0 rx_pkt_flt_mac_addr_prim_31to0 RW 32'h0
6-byte primary MAC address. You must map the address to the registers in the following manner:
  • rx_pkt_flt_mac_addr_prim_31to0 = Last four bytes of the address
  • rx_pkt_flt_mac_addr_prim_47to32: First two bytes of the address
0x06 15:0 rx_pkt_flt_mac_addr_prim_47to32 RW 16'h0
0x20 0 tx_fifo_clr RW 1'b0

Reset TX Egress TimeStamp FIFO.

1'b0: De-assert reset.

1'b1: Assert reset.
0x21 0 tx_fifo_ts_fprint_rdy RO 1'b0

Indicates the availability of the timestamp and the fingerprint.

1'b0: No timestamp and fingerprint available in the TX Egress Timsestamp FIFO.

1'b1: Timestamp and fingerprint available in the TX Egress Timestamp FIFO.

  16:8 tx_fifo_used_words RO 9'b0

Indicates the number of words in the FIFO.

0x25 31:0 tx_fifo_recovered_tstamp_31to0 RO 32'h0

The recovered timestamp.

For 96-bit timestamp format, all TX FIFO recovered timestamp register-sets are used.

For 64-bit timestamp format, only tx_fifo_recovered_tstamp_63to32 and tx_fifo_recovered_tstamp_31to0 registers are used.

Read to tx_fifo_recovered_tstamp_95to64 register indicates the completion of a read transaction for timestamp and fingerprint registers.

Altera recommend to follow the below order to read the timestamp and fingerprint registers:
  1. Read tx_fifo_recovered_fprint_31to0 register (optional).
  2. Read tx_fifo_recovered_tstamp_31to0 register.
  3. Read tx_fifo_recovered_tstamp_63to32 register.
  4. Read tx_fifo_recovered_tstamp_95to64 register.
0x26 31:0 tx_fifo_recovered_tstamp_63to32 RO 32'h0
0x27 31:0 tx_fifo_recovered_tstamp_95to64 RO 32'h0
0x28 19:0 tx_fifo_recovered_fprint_31to0 RW 20'h0

The fingerprint corresponding to the timestamp.

Read this register if the PTP stack is require to verify the timestamp correspond to the packet.

0x40 0 rx_fifo_clr RW 1'b0

Reset RX Ingress TimeStamp FIFO.

1'b0: De-assert reset.

1'b1: Assert reset.
0x41 0 rx_fifo_ts_fprint_rdy RO 1'b0

Indicates the availability of the timestamp and the fingerprint.

1'b0: No timestamp and fingerprint available in the RX Ingres Timestamp FIFO.

1'b1: Timestamp and fingerprint available in the RX Ingress Timestamp FIFO.

16:8 rx_fifo_used_words RO 9'b0

Indicates the number of words in the FIFO.

0x45 31:0 rx_fifo_recovered_tstamp_31to0 RO 32'h0

The recovered timestamp.

For 96-bit timestamp format, all RX FIFO recovered timestamp register-sets are used.

For 64-bit timestamp format, only rx_fifo_recovered_tstamp_63to32 and rx_fifo_recovered_tstamp_31to0 registers are used.

Read to rx_fifo_recovered_tstamp_95to64 register indicates the completion of a read transaction for timestamp and fingerprint registers.

Altera recommend to follow the below order to read the timestamp and fingerprint registers:
  1. Read rx_fifo_recovered_fprint_31to0 register (optional).
  2. Read rx_fifo_recovered_tstamp_31to0 register.
  3. Read rx_fifo_recovered_tstamp_63to32 register.
  4. Read Rx_fifo_recovered_tstamp_95to64 register.
0x46 31:0 rx_fifo_recovered_tstamp_63to32 RO 32'h0
0x47 31:0 rx_fifo_recovered_tstamp_95to64 RO 32'h0
0x48 19:0 rx_fifo_recovered_fprint_31to0 RW 20'h0

The fingerprint corresponding to the timestamp.

Read this register if the PTP stack is require to verify the timestamp correspond to the packet.

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