Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide

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ID 683447
Date 1/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview 2. Getting Started 3. Board Components A. Additional Information
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview x
1.1. Board Component Blocks 1.2. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable II Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: Intel® MAX® 10 FPGA 3.3. Configuration 3.4. Status Elements 3.5. Setup Elements 3.6. General User Input/Output 3.7. Clock Circuitry 3.8. Components and Interfaces
3.3. Configuration x
3.3.1. Using the Intel® Quartus® Prime Programmer 3.3.2. Selecting the Internal Configuration Scheme
3.7. Clock Circuitry x
3.7.1. On-Board Oscillators 3.7.2. Off-Board Clock Input/Output 3.7.3. Clock Control GUI
3.7.3. Clock Control GUI x
3.7.3.1. The Clock Control
3.8. Components and Interfaces x
3.8.1. HDMI Video Output 3.8.2. Pmod Connectors 3.8.3. Memory 3.8.4. Flash 3.8.5. MIPI CSI-2 Transmitter 3.8.6. MIPI CSI-2 Receiver 3.8.7. Power Supply
3.8.3. Memory x
3.8.3.1. LPDDR2
3.8.7. Power Supply x
3.8.7.1. Power Options 3.8.7.2. Power-Up Sequence
A. Additional Information x
A.1. Document Revision History for the Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide A.2. Safety and Regulatory Information A.3. Compliance Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview
2. Getting Started
3. Board Components
A. Additional Information

3.8.1. HDMI Video Output

The Intel® MAX® 10 10M50 evaluation kit supports one HDMI transmitter and one HDMI receptacle. The transmitter incorporates HDMI v1.4 features, and is capable of supporting an input data rate up to 165 MHz (1080p @ 60Hz, UXGA @ 60Hz). The connection between HDMI transmitter and Intel® MAX® 10 is established in Bank 7, and the communication can be done via I2C interface.

Table 18.  HDMI Pin Assignments, Signal Names and Functions
Board Reference (U3) Signal Name Intel® MAX® 10 FPGA Pin Number I/O Standard Description
U3.62 HDMI_VIDEO_DIN0 J12 3.3 V HDMI digital video data bus
U3.61 HDMI_VIDEO_DIN1 D13 3.3 V HDMI digital video data bus
U3.60 HDMI_VIDEO_DIN2 E12 3.3 V HDMI digital video data bus
U3.59 HDMI_VIDEO_DIN3 E13 3.3 V HDMI digital video data bus
U3.58 HDMI_VIDEO_DIN4 D12 3.3 V HDMI digital video data bus
U3.57 HDMI_VIDEO_DIN5 B16 3.3 V HDMI digital video data bus
U3.56 HDMI_VIDEO_DIN6 A16 3.3 V HDMI digital video data bus
U3.55 HDMI_VIDEO_DIN7 C15 3.3 V HDMI digital video data bus
U3.54 HDMI_VIDEO_DIN8 B14 3.3 V HDMI digital video data bus
U3.52 HDMI_VIDEO_DIN9 A14 3.3 V HDMI digital video data bus
U3.50 HDMI_VIDEO_DIN10 A13 3.3 V HDMI digital video data bus
U3.49 HDMI_VIDEO_DIN11 B12 3.3 V HDMI digital video data bus
U3.48 HDMI_VIDEO_DIN12 A12 3.3 V HDMI digital video data bus
U3.47 HDMI_VIDEO_DIN13 C12 3.3 V HDMI digital video data bus
U3.46 HDMI_VIDEO_DIN14 A11 3.3 V HDMI digital video data bus
U3.45 HDMI_VIDEO_DIN15 B11 3.3 V HDMI digital video data bus
U3.44 HDMI_VIDEO_DIN16 A10 3.3 V HDMI digital video data bus
U3.43 HDMI_VIDEO_DIN17 C14 3.3 V HDMI digital video data bus
U3.42 HDMI_VIDEO_DIN18 E14 3.3 V HDMI digital video data bus
U3.41 HDMI_VIDEO_DIN19 D14 3.3 V HDMI digital video data bus
U3.40 HDMI_VIDEO_DIN20 C13 3.3 V HDMI digital video data bus
U3.39 HDMI_VIDEO_DIN21 E15 3.3 V HDMI digital video data bus
U3.38 HDMI_VIDEO_DIN22 F15 3.3 V HDMI digital video data bus
U3.37 HDMI_VIDEO_DIN23 D15 3.3 V HDMI digital video data bus
U3.53 HDMI_VIDEO_CLK D6 3.3 V Video clock
U3.63 HDMI_VIDEO_DATA_EN J13 3.3 V Video data enable
U3.64 HDMI_HSYNC H13 3.3 V Vertical synchronization
U3.2 HDMI_VSYNC H14 3.3 V Horizontal synchronization
U3.28 HDMI_INTR A18 3.3 V Interrupt signal
U3.35 HDMI_SCL C16 3.3 V HDMI I2C clock
U3.36 HDMI_SDA B17 3.3 V HDMI I2C data
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