Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide

Download PDF
ID 683447
Date 1/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview 2. Getting Started 3. Board Components A. Additional Information
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview x
1.1. Board Component Blocks 1.2. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable II Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: Intel® MAX® 10 FPGA 3.3. Configuration 3.4. Status Elements 3.5. Setup Elements 3.6. General User Input/Output 3.7. Clock Circuitry 3.8. Components and Interfaces
3.3. Configuration x
3.3.1. Using the Intel® Quartus® Prime Programmer 3.3.2. Selecting the Internal Configuration Scheme
3.7. Clock Circuitry x
3.7.1. On-Board Oscillators 3.7.2. Off-Board Clock Input/Output 3.7.3. Clock Control GUI
3.7.3. Clock Control GUI x
3.7.3.1. The Clock Control
3.8. Components and Interfaces x
3.8.1. HDMI Video Output 3.8.2. Pmod Connectors 3.8.3. Memory 3.8.4. Flash 3.8.5. MIPI CSI-2 Transmitter 3.8.6. MIPI CSI-2 Receiver 3.8.7. Power Supply
3.8.3. Memory x
3.8.3.1. LPDDR2
3.8.7. Power Supply x
3.8.7.1. Power Options 3.8.7.2. Power-Up Sequence
A. Additional Information x
A.1. Document Revision History for the Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide A.2. Safety and Regulatory Information A.3. Compliance Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview
2. Getting Started
3. Board Components
A. Additional Information

3.8.2. Pmod Connectors

The Intel® MAX® 10 10M50 Evaluation Kit features two Digilent Pmod™ compatible headers, which are used to connect low frequency, low I/O pin count peripheral modules.

The 12-pin version Pmod connector used in this kit provides 8 I/O signal pins. The peripheral module interface also encompasses a variant using I2C interface, and two or four wire MTE cables. The Pmod signals are connected to Bank 8.

Table 19.  Pmod A Pin Assignments, Signal Names and Functions
Schematic Signal Name Schematic Share Bus Signal Name Intel® MAX® 10 FPGA Pin Number I/O Standard Description
PMODA_D0 PMODA_IO0 A6 3.3 V In/Out
PMODA_D1 PMODA_IO1 E8 3.3 V In/Out
PMODA_D2 PMODA_IO2 B4 3.3 V In/Out
PMODA_D3 PMODA_IO3 A5 3.3 V In/Out
PMODA_D4 PMODA_IO4 B7 3.3 V In/Out
PMODA_D5 PMODA_IO5 E9 3.3 V In/Out
PMODA_D6 PMODA_IO6 A4 3.3 V In/Out
PMODA_D7 PMODA_IO7 B5 3.3 V In/Out
--- VCC --- 3.3 V Power
--- GND --- --- GND
Table 20.  Pmod B Pin Assignments, Signal Names and Functions
Schematic Signal Name Schematic Share Bus Signal Name Intel® MAX® 10 FPGA Pin Number I/O Standard Description
PMODB_D0 PMODB_IO0 C8 3.3 V In/Out
PMODB_D1 PMODB_IO1 D8 3.3 V In/Out
PMODB_D2 PMODB_IO2 A3 3.3 V In/Out
PMODB_D3 PMODB_IO3 A2 3.3 V In/Out
PMODB_D4 PMODB_IO4 B3 3.3 V In/Out
PMODB_D5 PMODB_IO5 C2 3.3 V In/Out
PMODB_D6 PMODB_IO6 B1 3.3 V In/Out
PMODB_D7 PMODB_IO7 B2 3.3 V In/Out
--- VCC --- 3.3 V Power
--- GND --- --- GND
Level Two Title