E-Tile Transceiver PHY User Guide

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ID 683723
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. E-Tile Transceiver PHY Overview 2. Implementing the Transceiver PHY Layer 3. E-Tile Transceiver PHY Architecture 4. Clock Network 5. PMA Calibration 6. Resetting Transceiver Channels 7. Dynamic Reconfiguration 8. Dynamic Reconfiguration Examples 9. Register Map 10. Debugging E-Tile Transceiver Links A. E-Tile Channel Placement Tool B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation C. Signal Detect Algorithm D. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode E. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode F. Hold Timing Violation
1. E-Tile Transceiver PHY Overview x
1.1. Supported Features 1.2. E-Tile Layout in Stratix® 10 Device Variants 1.3. E-Tile Layout in Agilex™ 7 F-Series Device Variants 1.4. Transceiver Counts 1.5. E-Tile Building Blocks 1.6. E-Tile Transceiver PHY Overview Revision History
1.2. E-Tile Layout in Stratix® 10 Device Variants x
1.2.1. Stratix® 10 TX H-Tile and E-Tile Configurations 1.2.2. Stratix® 10 MX H-Tile and E-Tile Configurations 1.2.3. Stratix® 10 DX P-Tile and E-Tile Configurations
1.5. E-Tile Building Blocks x
1.5.1. GXE Transceiver Channel 1.5.2. GXE Channel Usage 1.5.3. Reference Clocks 1.5.4. Ethernet Hard IP (EHIP) 1.5.5. Supported Applications/Modes 1.5.6. Feature Comparison Between Transceiver Tiles
2. Implementing the Transceiver PHY Layer x
2.1. Transceiver Design Flow in the Native PHY IP Core 2.2. Configuring the Native PHY IP Core 2.3. Implementing the Transceiver PHY Layer Revision History
2.1. Transceiver Design Flow in the Native PHY IP Core x
2.1.1. E-Tile Native PHY IP Core
2.2. Configuring the Native PHY IP Core x
2.2.1. General and Datapath Parameters 2.2.2. PMA Parameters 2.2.3. Core Interface Options 2.2.4. PMA Interface 2.2.5. PMA Adaptation Parameters 2.2.6. Reed Solomon Forward Error Correction (RS-FEC) Parameters 2.2.7. Reset Parameters 2.2.8. Dynamic Reconfiguration Parameters 2.2.9. Deskew Logic 2.2.10. Port Information 2.2.11. PLL Mode 2.2.12. Simplex Support
2.2.2. PMA Parameters x
2.2.2.1. TX PMA Options 2.2.2.2. TX PMA Pre-equalization 2.2.2.3. RX PMA Options 2.2.2.4. RX PMA Optional Ports
2.2.3. Core Interface Options x
2.2.3.1. Core Interface Parameters 2.2.3.2. TX Clock Options 2.2.3.3. RX Clock Options 2.2.3.4. Latency Measurement Options
2.2.4. PMA Interface x
2.2.4.1. PMA Interface Options 2.2.4.2. Gearbox 64/66
2.2.6. Reed Solomon Forward Error Correction (RS-FEC) Parameters x
2.2.6.1. Fibre-Channel and CPRI Modes 2.2.6.2. 128 GFC Mode 2.2.6.3. 25 GbE FEC Direct Mode 2.2.6.4. Interlaken Mode
3. E-Tile Transceiver PHY Architecture x
3.1. Physical Medium Attachment (PMA) Architecture 3.2. Physical Coding Sublayer (PCS) Architecture 3.3. Reed Solomon Forward Error Correction (RS-FEC) Architecture 3.4. E-Tile Transceiver PHY Architecture Revision History
3.1. Physical Medium Attachment (PMA) Architecture x
3.1.1. Transmitter PMA 3.1.2. Receiver PMA 3.1.3. PMA Tuning 3.1.4. Duplex Adaptation Flow 3.1.5. RX Simplex Adaptation Flow 3.1.6. Dynamic Reconfiguration Adaptation Flow 3.1.7. Loopback modes 3.1.8. PMA Interface 3.1.9. TX PMA Bonding 3.1.10. Unused Transceiver Channels 3.1.11. Low Power Mode (LPM)
3.1.1. Transmitter PMA x
3.1.1.1. High Speed Differential Transmitter 3.1.1.2. Gray Encoder/Precoder 3.1.1.3. Serializer 3.1.1.4. Data Pattern Generation
3.1.1.1. High Speed Differential Transmitter x
3.1.1.1.1. High Speed Transmitter Line Buffer 3.1.1.1.2. TX Equalizer
3.1.2. Receiver PMA x
3.1.2.1. Receiver Buffer 3.1.2.2. Clock Data Recovery (CDR) Block 3.1.2.3. Input Sampler 3.1.2.4. Deserializer 3.1.2.5. Data Pattern Verifier
3.1.2.1. Receiver Buffer x
3.1.2.1.1. Programmable Termination Modes 3.1.2.1.2. RX Adaptation Modes
3.1.3. PMA Tuning x
3.1.3.1. Purpose of PMA Tuning 3.1.3.2. PMA Bring Up Flow 3.1.3.3. PMA Tuning Guidelines 3.1.3.4. General PMA Tuning Guidelines
3.1.7. Loopback modes x
3.1.7.1. Internal Serial Loopback Path 3.1.7.2. Reverse Parallel Loopback Path
3.1.9. TX PMA Bonding x
3.1.9.1. Transceiver Interface Deskew Logic 3.1.9.2. Dedicated Balanced PLL Reference Clock Tree
3.1.10. Unused Transceiver Channels x
3.1.10.1. Unused Transceiver Channels in a Used Tile 3.1.10.2. Unused Transceiver Channels in Completely Unused Tiles 3.1.10.3. Unused Transceiver Channels in High-Speed PAM4 Mode 3.1.10.4. Reconfiguring from Mission Mode to Channel Protection Mode 3.1.10.5. Reconfiguring from Channel Protection Mode to Mission Mode
3.3. Reed Solomon Forward Error Correction (RS-FEC) Architecture x
3.3.1. RS-FEC Modes
4. Clock Network x
4.1. Reference Clock Pins 4.2. Core Clock Network Use Case 4.3. Clock Network Revision History
4.1. Reference Clock Pins x
4.1.1. QSF Assignments for Reference Clock Pins 4.1.2. Dynamic Reconfiguration of Reference Clock
4.2. Core Clock Network Use Case x
4.2.1. Single 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC Block 4.2.2. Single 10 Gbps PMA Direct Channel (without FEC) 4.2.3. Four 25 Gbps PMA Direct Channel (with FEC) within a Single FEC Block 4.2.4. PMA Direct 25 Gbps x 4 (FEC Off) 4.2.5. PMA Direct 10.3125 Gbps x 4 4.2.6. PMA Direct 100GE Gbps (25 Gbps x 4) (FEC On) 4.2.7. PMA Direct 100GE PAM4 (50 Gbps x 2) (Aggregate FEC On) 4.2.8. PMA Direct High Data Rate (FEC Off)
4.2.3. Four 25 Gbps PMA Direct Channel (with FEC) within a Single FEC Block x
4.2.3.1. Master-Slave Configuration: Option 1 4.2.3.2. Master-Slave Configuration: Option 2
5. PMA Calibration x
5.1. PMA Calibration Revision History
6. Resetting Transceiver Channels x
6.1. When Is Reset Required? 6.2. How Do I Reset? 6.3. Reset Block Architecture 6.4. PMA Analog Reset 6.5. High Level Specification 6.6. Master-Slave Clocking Option 2 Reset Details 6.7. Quartus® Prime Instantiated Transceiver Reset Sequencer 6.8. Block Diagrams 6.9. Interfaces 6.10. Resetting Transceiver Channels Revision History
6.2. How Do I Reset? x
6.2.1. Disabling the E-Tile Transceiver 6.2.2. Selecting the Reset Controller's Clock Source
6.5. High Level Specification x
6.5.1. Automatic Reset Mode 6.5.2. Manual Reset Mode 6.5.3. Reset Controller Bypass
6.5.3. Reset Controller Bypass x
6.5.3.1. Reset Controller Bypass Ports 6.5.3.2. Reset Controller Bypass Reset Procedure
6.9. Interfaces x
6.9.1. Reset Parameters in the Native PHY GUI 6.9.2. HDL Ports/Interfaces
7. Dynamic Reconfiguration x
7.1. Dynamically Reconfiguring Channel Blocks 7.2. Dynamic Reconfiguration Maximum Data Rate Switch 7.3. Interacting with the Dynamic Reconfiguration Interface 7.4. Unsupported Features 7.5. Reading from the Dynamic Reconfiguration Interface 7.6. Writing to the Dynamic Reconfiguration Interface 7.7. Multiple Reconfiguration Profiles 7.8. Arbitration 7.9. Recommendations for PMA Dynamic Reconfiguration 7.10. Steps to Perform Dynamic Reconfiguration 7.11. PMA Attribute Details 7.12. Dynamic Reconfiguration Flow for Special Cases 7.13. Ports and Parameters 7.14. Embedded Debug Features 7.15. Timing Closure Recommendations 7.16. Transceiver Register Map 7.17. Loading IP Configuration Settings 7.18. Dynamic Reconfiguration Revision History
7.7. Multiple Reconfiguration Profiles x
7.7.1. Reconfiguration Files 7.7.2. Embedded Reconfiguration Streamer
7.7.2. Embedded Reconfiguration Streamer x
7.7.2.1. Register 0x40140 7.7.2.2. Register 0x40141
7.12. Dynamic Reconfiguration Flow for Special Cases x
7.12.1. Switching Reference Clocks 7.12.2. Reconfiguring PMA Settings
7.12.1. Switching Reference Clocks x
7.12.1.1. Switching Between Any Two refclk[0, 1, 2, 3, 4, 5, 6, 7] Reference Clocks or Changing the Reference Clock Frequency on refclk[0, 2, 3, 4, 5, 6, 7, 8] 7.12.1.2. Switching from/to refclk[0, 1, 2, 3, 4, 5, 6, 7] to/from refclk[8] 7.12.1.3. Changing the refclk[1] Reference Clock Frequency
7.14. Embedded Debug Features x
7.14.1. Native PHY Debug Master Endpoint (NPDME) 7.14.2. Optional Dynamic Reconfiguration Logic
7.14.2. Optional Dynamic Reconfiguration Logic x
7.14.2.1. Capability Registers 7.14.2.2. Control and Status Registers
7.17. Loading IP Configuration Settings x
7.17.1. Loading IP Configuration Settings Process 7.17.2. Alternative Method for Setting PMA Attributes
8. Dynamic Reconfiguration Examples x
8.1. Reconfiguring the Duplex PMA Using the Reset Controller in Automatic Mode 8.2. PRBS Usage Model 8.3. PMA Error Injection 8.4. PMA Receiver Equalization Adaptation Usage Model 8.5. User-Defined Pattern Example 8.6. Configuring the Attenuation Value (VOD) 8.7. Configuring the Post Emphasis Value 8.8. Configuring pretap1 Values 8.9. Inverting TX Polarity for the PMA Driver 8.10. Inverting RX Polarity for the PMA Driver 8.11. Configuring a PMA Parameter Tunable by the Adaptive Engine 8.12. Configuring a PMA Parameter Using Native PHY IP 8.13. Enabling Low Power Mode for Multiple Channels 8.14. Initializing an RX 8.15. Resetting the RX Equalization 8.16. Dynamic Reconfiguration Examples Revision History
8.12. Configuring a PMA Parameter Using Native PHY IP x
8.12.1. PMA Bring Up Flow Using Native PHY IP 8.12.2. Native PHY IP GUI Details 8.12.3. Loading a PMA Configuration
9. Register Map x
9.1. PMA Register Map 9.2. PMA Attribute Codes 9.3. PMA Registers 0x200 to 0x203 Usage 9.4. Supported Data Rate Ratios for PMA Attribute Codes 0x0005 and 0x0006 9.5. RS-FEC Registers 9.6. Register Map Revision History
9.1. PMA Register Map x
9.1.1. PMA Capability Registers 9.1.2. PMA Control and Status Registers 9.1.3. PMA Avalon® Memory-Mapped Interface
9.2. PMA Attribute Codes x
9.2.1. 0x0001: PMA Enable/Disable 9.2.2. 0x0002: PMA PRBS Settings 9.2.3. 0x0003: Data Comparison Set Up and Start/Stop 9.2.4. 0x0005: TX Channel Divide By Ratio 9.2.5. 0x0006: RX Channel Divide By Ratio 9.2.6. 0x0008: Internal Serial Loopback and Reverse Parallel Loopback Control 9.2.7. 0x000A: Receiver Tuning Controls 9.2.8. 0x000E: RX Phase Slip 9.2.9. 0x0011: PMA TX/RX Calibration 9.2.10. 0x0013: TX/RX Polarity and Gray Code Encoding 9.2.11. 0x0014: TX/RX Width Mode 9.2.12. 0x0015: TX Equalization 9.2.13. 0x0017: Error Counter Reset 9.2.14. 0x0018: Status/Debug Register 9.2.15. 0x0019: Status/Debug Register Next Write Field 9.2.16. 0x001A: Status/Debug Register Next Read Field 9.2.17. 0x001B: TX Error Injection Signal 9.2.18. 0x001C: Incoming RX Data Capture 9.2.19. 0x001E: Error Count Status 9.2.20. 0x0020: Electrical Idle Detector 9.2.21. 0x002B: RX Termination and TX Driver Tri-state Behavior 9.2.22. 0x0030: PMA Mux Clock Swap 9.2.23. 0x0126: Read Receiver Tuning Parameters 9.2.24. Reading and Writing PMA Analog Parameters Using Attributes
9.2.24. Reading and Writing PMA Analog Parameters Using Attributes x
9.2.24.1. Reading PMA Analog Parameters 9.2.24.2. Updating PMA Analog Parameters 9.2.24.3. Loading Parameters into the Receiver 9.2.24.4. Fixing Parameter Values 9.2.24.5. Reading NRZ/PAM4 Eye Height 9.2.24.6. Enabling and Disabling Electrical Idle Detector Filtering and Reading Electrical Idle Detector Status 9.2.24.7. Initial Adaptation Effort Levels
9.3. PMA Registers 0x200 to 0x203 Usage x
9.3.1. PMA Analog Reset 9.3.2. Set PRBS Mode and Internal Serial Loopback 9.3.3. Use Cases for Opcode START_ADAPTATION 9.3.4. Read the Physical Channel Number 9.3.5. Check the PMA Adaptation Status 9.3.6. Load a PMA Configuration using Opcode LOAD_PMA_CONFIGURATION
9.5. RS-FEC Registers x
9.5.1. rsfec_top_clk_cfg 9.5.2. rsfec_top_tx_cfg 9.5.3. rsfec_top_rx_cfg 9.5.4. tx_aib_dsk_conf 9.5.5. rsfec_core_cfg 9.5.6. rsfec_lane_cfg 9.5.7. tx_aib_dsk_status 9.5.8. rsfec_debug_cfg 9.5.9. rsfec_lane_tx_stat 9.5.10. rsfec_lane_tx_hold 9.5.11. rsfec_lane_tx_inten 9.5.12. rsfec_lane_rx_stat 9.5.13. rsfec_lane_rx_hold 9.5.14. rsfec_lane_rx_inten 9.5.15. rsfec_lanes_rx_stat 9.5.16. rsfec_lanes_rx_hold 9.5.17. rsfec_lanes_rx_inten 9.5.18. rsfec_ln_mapping_rx 9.5.19. rsfec_ln_skew_rx 9.5.20. rsfec_cw_pos_rx 9.5.21. rsfec_core_ecc_hold 9.5.22. rsfec_err_inj_tx 9.5.23. rsfec_err_val_tx 9.5.24. rsfec_corr_cw_cnt (Low) 9.5.25. rsfec_corr_cw_cnt (High) 9.5.26. rsfec_uncorr_cw_cnt (Low) 9.5.27. rsfec_uncorr_cw_cnt (High) 9.5.28. rsfec_corr_syms_cnt (Low) 9.5.29. rsfec_corr_syms_cnt (High) 9.5.30. rsfec_corr_0s_cnt (Low) 9.5.31. rsfec_corr_0s_cnt (High) 9.5.32. rsfec_corr_1s_cnt (Low) 9.5.33. rsfec_corr_1s_cnt (High)
10. Debugging E-Tile Transceiver Links x
10.1. E-Tile Transceiver Toolkit Overview 10.2. E-Tile Transceiver Debugging Flow Walkthrough 10.3. Modifying the Design to Enable E-Tile Transceiver Debug 10.4. Programming the Design into an Intel FPGA 10.5. Loading the Design in the E-Tile Transceiver Toolkit 10.6. Verifying E-Tile Hardware Connections 10.7. Running Transceiver Tests 10.8. Controlling PMA Analog Settings 10.9. Debugging E-Tile Transceiver Links Revision History
10.3. Modifying the Design to Enable E-Tile Transceiver Debug x
10.3.1. Debug Parameters for the E-Tile Transceiver IP in the Parameter Editor 10.3.2. Debug Parameters for Stratix® 10 E-Tile Transceiver Native PHY IP in the Parameter Editor 10.3.3. Instantiating and Parameterizing E-Tile Transceiver IP
10.7. Running Transceiver Tests x
10.7.1. Running BER Tests 10.7.2. Link Optimization Tests 10.7.3. Running Eye Viewer Tests
A. E-Tile Channel Placement Tool x
A.1. E-Tile Channel Placement Tool Revision History
B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation x
B.1. Building Blocks and Considerations B.2. Starting a New Quartus® Prime Pro Edition Design B.3. Selecting the Configuration Clock Source B.4. Instantiating the Transceiver Native PHY IP B.5. Instantiating the In-system Sources and Probes Intel® FPGA IP B.6. Making the Top Level Connection B.7. Assigning Pins B.8. Bringing up the Board B.9. Debug Tools B.10. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation Revision History
B.9. Debug Tools x
B.9.1. Monitoring Transceiver Signals
C. Signal Detect Algorithm x
C.1. Signal Detect Algorithm Revision History
D. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode x
D.1. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode Revision History
E. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode x
E.1. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode Revision History
F. Hold Timing Violation x
F.1. Hold Timing Violation Revision History
1. E-Tile Transceiver PHY Overview
2. Implementing the Transceiver PHY Layer
3. E-Tile Transceiver PHY Architecture
4. Clock Network
5. PMA Calibration
6. Resetting Transceiver Channels
7. Dynamic Reconfiguration
8. Dynamic Reconfiguration Examples
9. Register Map
10. Debugging E-Tile Transceiver Links
A. E-Tile Channel Placement Tool
B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation
C. Signal Detect Algorithm
D. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode
E. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode
F. Hold Timing Violation

8.1. Reconfiguring the Duplex PMA Using the Reset Controller in Automatic Mode

Dynamic reconfiguration is the process of modifying transceiver channels to meet changing requirements during device operation. You can customize channels by initiating reconfiguration during device operation or after device configuration.
Common PMA parameters that are reconfigured are the reference clock source, data rate and PMA serialization/deserialization factor. Refer to PMA Attribute Codes for how to change the attribute codes. The following example shows how to reconfigure a duplex PMA channel in NRZ mode in order to:
  • Reconfigure the PMA reference clock from refclk0 to refclk1 as listed in the Native PHY IP
  • Change the PMA baud rate
  • Change the deserialization factor
Figure 109. Sending PMA Attribute Through Avalon® Memory-Mapped Interface

Reconfiguration Flow

  1. Assert tx_reset/rx_reset.
  2. Wait for the tx_ready/rx_ready to deassert.
  3. Disable the PMA by using PMA attribute code 0x0001.
    1. Optional: Write 0x8A[7] = 0x1 to ensure the PMA attribute status flag (0x8A[7] for the previous attribute) is cleared before writing to registers 0x84 to 0x87 to load in the new PMA attribute.
    2. Write 0x84[7:0] = 0x00.
    3. Write 0x85[7:0] = 0x00.
    4. Write 0x86[7:0] = 0x01.
    5. Write 0x87[7:0] = 0x00.
    6. Write 0x90[0] = 1’b1.
    7. Read 0x8A[7]. It should be 1.
    8. Read 0x8B[0] until it changes to 0.
    9. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  4. Wait for tx_pma_ready/rx_pma_ready to deassert.
  5. Refer to Switching Reference Clocks for how to change the reference clock.
  6. Reset the internal controller inside the PMA because the REFCLK source changed by:
    1. Write 0x200[7:0] = 0x00.
    2. Write 0x201[7:0] = 0x00.
    3. Write 0x202[7:0] = 0x00.
    4. Write 0x203[7:0] = 0x81.
    5. Read 0x207 until it becomes 0x80. This indicates that the operation completed successfully.
  7. Change TX/RX baud rate to refclk * 50 and above 15 Gbps by using PMA attribute code 0x0005.
    1. Write 0x84[7:0] = 0x32.
    2. Write 0x85[7:0] = 0x80 (bit 7 applies the update to both TX/RX).
    3. Write 0x86[7:0] = 0x05.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1’b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  8. Change serialization/deserialization factor to 40 bits wide by using PMA attribute code 0x0014.
    1. Write 0x84[7:0] = 0x33.
    2. Write 0x85[7:0] =0x00.
    3. Write 0x86[7:0] = 0x14.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1’b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  9. Change the RX phase slip to maximize the RX PMA timing margin.
    1. Write 0x84[7:0] = 0x00.
    2. Write 0x85[7:0] = 0xA4 to slip by 36 UI.
    3. Write 0x86[7:0] = 0x0E.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1’b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  10. Enable the PMA by using PMA attribute code 0x0001.
    1. Write 0x84[7:0] = 0x07.
    2. Write 0x85[7:0] =0x00.
    3. Write 0x86[7:0] = 0x01.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1’b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  11. Enable PRBS31 data.
    1. Write 0x84[7:0] = 0x25.
    2. Write 0x85[7:0] = 0x03.
    3. Write 0x86[7:0] = 0x02.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  12. Change to internal serial loopback mode by using PMA attribute code 0x0008.
    1. Write 0x84[7:0] = 0x01.
    2. Write 0x85[7:0] = 0x01.
    3. Write 0x86[7:0] = 0x08.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1’b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  13. Enable initial coarse adaptive equalization by using PMA attribute code 0x000A.
    1. Write 0x84[7:0] = 0x01.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x0A.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  14. Read initial coarse adaptation status by using PMA attribute code 0x0126.
    1. Write 0x84[7:0] = 0x00.
    2. Write 0x85[7:0] = 0x0B.
    3. Write 0x86[7:0] = 0x26.
    4. Write 0x87[7:0] = 0x01.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
    9. Read register 0x88. Repeat current step 14 until 0x88[0] =0 to indicate that initial coarse adaptation has completed.
  15. If you are using a stored PMA configuration, first choose the PMA configuration.
    1. Write 0x40143 = (0x80 + configuration number you want to load). For example, write value 0x82 to load configuration 2. You can access the stored PMA configurations only from channel 0.
    2. Read 0x40144[0] until it reports 0x1.
  16. If using a stored PMA configuration, load the configuration into the transceiver channel using opcode 0x14.
    1. Write 0x200 = 0x00.
    2. Write 0x201 = 0x00.
    3. Write 0x202 = 0x00.
    4. Write 0x203 = 0x94.
    5. Poll 0x207 until = 0x80.

Skip the next step if you are running internal serial loopback mode.

  1. Disable Internal Serial Loopback using PMA attributes.
    1. Write 0x84[7:0] = 0x00.
    2. Write 0x85[7:0] = 0x01.
    3. Write 0x86[7:0] = 0x08.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.

Skip the next step if you are running internal serial loopback mode.

  1. Perform initial adaptation using PMA attributes.
    1. Write 0x84[7:0] = 0x01.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x0A.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  2. Deassert tx_reset/rx_reset.
  3. Disable PRBS31 data using opcode 0x13.
    1. If in mission mode, write 0x200 = 0x1E.
    2. If in internal serial loopback mode, write 0x200 = 0x1F.
    3. Write 0x201 = 0x00.
    4. Write 0x202 = 0x00.
    5. Write 0x203 = 0x93.
    6. Read 0x207 until it becomes 0x80. This indicates that the operation completed successfully.
  4. If valid data rate traffic is available at RX, go to the next step, or re-run initial coarse adaptation until the traffic is valid.
  5. If you need to set a PMA analog parameter before running continuous adaptation, send the attributes. Refer to Reading and Writing PMA Analog Parameters Using Attributes.
  6. Enable continuous adaptive equalization by using PMA attribute code 0x000A.
    1. Write 0x84[7:0] = 0x06.
    2. Write 0x85[7:0] = 0x00.
    3. Write 0x86[7:0] = 0x0A.
    4. Write 0x87[7:0] = 0x00.
    5. Write 0x90[0] = 1'b1.
    6. Read 0x8A[7]. It should be 1.
    7. Read 0x8B[0] until it changes to 0.
    8. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
  7. Optionally, check the rx_is_lockedtodata output pin.
  8. The link is up.
Related Information
Level Two Title