E-Tile Transceiver PHY User Guide

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ID 683723
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. E-Tile Transceiver PHY Overview 2. Implementing the Transceiver PHY Layer 3. E-Tile Transceiver PHY Architecture 4. Clock Network 5. PMA Calibration 6. Resetting Transceiver Channels 7. Dynamic Reconfiguration 8. Dynamic Reconfiguration Examples 9. Register Map 10. Debugging E-Tile Transceiver Links A. E-Tile Channel Placement Tool B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation C. Signal Detect Algorithm D. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode E. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode F. Hold Timing Violation
1. E-Tile Transceiver PHY Overview x
1.1. Supported Features 1.2. E-Tile Layout in Stratix® 10 Device Variants 1.3. E-Tile Layout in Agilex™ 7 F-Series Device Variants 1.4. Transceiver Counts 1.5. E-Tile Building Blocks 1.6. E-Tile Transceiver PHY Overview Revision History
1.2. E-Tile Layout in Stratix® 10 Device Variants x
1.2.1. Stratix® 10 TX H-Tile and E-Tile Configurations 1.2.2. Stratix® 10 MX H-Tile and E-Tile Configurations 1.2.3. Stratix® 10 DX P-Tile and E-Tile Configurations
1.5. E-Tile Building Blocks x
1.5.1. GXE Transceiver Channel 1.5.2. GXE Channel Usage 1.5.3. Reference Clocks 1.5.4. Ethernet Hard IP (EHIP) 1.5.5. Supported Applications/Modes 1.5.6. Feature Comparison Between Transceiver Tiles
2. Implementing the Transceiver PHY Layer x
2.1. Transceiver Design Flow in the Native PHY IP Core 2.2. Configuring the Native PHY IP Core 2.3. Implementing the Transceiver PHY Layer Revision History
2.1. Transceiver Design Flow in the Native PHY IP Core x
2.1.1. E-Tile Native PHY IP Core
2.2. Configuring the Native PHY IP Core x
2.2.1. General and Datapath Parameters 2.2.2. PMA Parameters 2.2.3. Core Interface Options 2.2.4. PMA Interface 2.2.5. PMA Adaptation Parameters 2.2.6. Reed Solomon Forward Error Correction (RS-FEC) Parameters 2.2.7. Reset Parameters 2.2.8. Dynamic Reconfiguration Parameters 2.2.9. Deskew Logic 2.2.10. Port Information 2.2.11. PLL Mode 2.2.12. Simplex Support
2.2.2. PMA Parameters x
2.2.2.1. TX PMA Options 2.2.2.2. TX PMA Pre-equalization 2.2.2.3. RX PMA Options 2.2.2.4. RX PMA Optional Ports
2.2.3. Core Interface Options x
2.2.3.1. Core Interface Parameters 2.2.3.2. TX Clock Options 2.2.3.3. RX Clock Options 2.2.3.4. Latency Measurement Options
2.2.4. PMA Interface x
2.2.4.1. PMA Interface Options 2.2.4.2. Gearbox 64/66
2.2.6. Reed Solomon Forward Error Correction (RS-FEC) Parameters x
2.2.6.1. Fibre-Channel and CPRI Modes 2.2.6.2. 128 GFC Mode 2.2.6.3. 25 GbE FEC Direct Mode 2.2.6.4. Interlaken Mode
3. E-Tile Transceiver PHY Architecture x
3.1. Physical Medium Attachment (PMA) Architecture 3.2. Physical Coding Sublayer (PCS) Architecture 3.3. Reed Solomon Forward Error Correction (RS-FEC) Architecture 3.4. E-Tile Transceiver PHY Architecture Revision History
3.1. Physical Medium Attachment (PMA) Architecture x
3.1.1. Transmitter PMA 3.1.2. Receiver PMA 3.1.3. PMA Tuning 3.1.4. Duplex Adaptation Flow 3.1.5. RX Simplex Adaptation Flow 3.1.6. Dynamic Reconfiguration Adaptation Flow 3.1.7. Loopback modes 3.1.8. PMA Interface 3.1.9. TX PMA Bonding 3.1.10. Unused Transceiver Channels 3.1.11. Low Power Mode (LPM)
3.1.1. Transmitter PMA x
3.1.1.1. High Speed Differential Transmitter 3.1.1.2. Gray Encoder/Precoder 3.1.1.3. Serializer 3.1.1.4. Data Pattern Generation
3.1.1.1. High Speed Differential Transmitter x
3.1.1.1.1. High Speed Transmitter Line Buffer 3.1.1.1.2. TX Equalizer
3.1.2. Receiver PMA x
3.1.2.1. Receiver Buffer 3.1.2.2. Clock Data Recovery (CDR) Block 3.1.2.3. Input Sampler 3.1.2.4. Deserializer 3.1.2.5. Data Pattern Verifier
3.1.2.1. Receiver Buffer x
3.1.2.1.1. Programmable Termination Modes 3.1.2.1.2. RX Adaptation Modes
3.1.3. PMA Tuning x
3.1.3.1. Purpose of PMA Tuning 3.1.3.2. PMA Bring Up Flow 3.1.3.3. PMA Tuning Guidelines 3.1.3.4. General PMA Tuning Guidelines
3.1.7. Loopback modes x
3.1.7.1. Internal Serial Loopback Path 3.1.7.2. Reverse Parallel Loopback Path
3.1.9. TX PMA Bonding x
3.1.9.1. Transceiver Interface Deskew Logic 3.1.9.2. Dedicated Balanced PLL Reference Clock Tree
3.1.10. Unused Transceiver Channels x
3.1.10.1. Unused Transceiver Channels in a Used Tile 3.1.10.2. Unused Transceiver Channels in Completely Unused Tiles 3.1.10.3. Unused Transceiver Channels in High-Speed PAM4 Mode 3.1.10.4. Reconfiguring from Mission Mode to Channel Protection Mode 3.1.10.5. Reconfiguring from Channel Protection Mode to Mission Mode
3.3. Reed Solomon Forward Error Correction (RS-FEC) Architecture x
3.3.1. RS-FEC Modes
4. Clock Network x
4.1. Reference Clock Pins 4.2. Core Clock Network Use Case 4.3. Clock Network Revision History
4.1. Reference Clock Pins x
4.1.1. QSF Assignments for Reference Clock Pins 4.1.2. Dynamic Reconfiguration of Reference Clock
4.2. Core Clock Network Use Case x
4.2.1. Single 25 Gbps PMA Direct Channel (with FEC) Within a Single FEC Block 4.2.2. Single 10 Gbps PMA Direct Channel (without FEC) 4.2.3. Four 25 Gbps PMA Direct Channel (with FEC) within a Single FEC Block 4.2.4. PMA Direct 25 Gbps x 4 (FEC Off) 4.2.5. PMA Direct 10.3125 Gbps x 4 4.2.6. PMA Direct 100GE Gbps (25 Gbps x 4) (FEC On) 4.2.7. PMA Direct 100GE PAM4 (50 Gbps x 2) (Aggregate FEC On) 4.2.8. PMA Direct High Data Rate (FEC Off)
4.2.3. Four 25 Gbps PMA Direct Channel (with FEC) within a Single FEC Block x
4.2.3.1. Master-Slave Configuration: Option 1 4.2.3.2. Master-Slave Configuration: Option 2
5. PMA Calibration x
5.1. PMA Calibration Revision History
6. Resetting Transceiver Channels x
6.1. When Is Reset Required? 6.2. How Do I Reset? 6.3. Reset Block Architecture 6.4. PMA Analog Reset 6.5. High Level Specification 6.6. Master-Slave Clocking Option 2 Reset Details 6.7. Quartus® Prime Instantiated Transceiver Reset Sequencer 6.8. Block Diagrams 6.9. Interfaces 6.10. Resetting Transceiver Channels Revision History
6.2. How Do I Reset? x
6.2.1. Disabling the E-Tile Transceiver 6.2.2. Selecting the Reset Controller's Clock Source
6.5. High Level Specification x
6.5.1. Automatic Reset Mode 6.5.2. Manual Reset Mode 6.5.3. Reset Controller Bypass
6.5.3. Reset Controller Bypass x
6.5.3.1. Reset Controller Bypass Ports 6.5.3.2. Reset Controller Bypass Reset Procedure
6.9. Interfaces x
6.9.1. Reset Parameters in the Native PHY GUI 6.9.2. HDL Ports/Interfaces
7. Dynamic Reconfiguration x
7.1. Dynamically Reconfiguring Channel Blocks 7.2. Dynamic Reconfiguration Maximum Data Rate Switch 7.3. Interacting with the Dynamic Reconfiguration Interface 7.4. Unsupported Features 7.5. Reading from the Dynamic Reconfiguration Interface 7.6. Writing to the Dynamic Reconfiguration Interface 7.7. Multiple Reconfiguration Profiles 7.8. Arbitration 7.9. Recommendations for PMA Dynamic Reconfiguration 7.10. Steps to Perform Dynamic Reconfiguration 7.11. PMA Attribute Details 7.12. Dynamic Reconfiguration Flow for Special Cases 7.13. Ports and Parameters 7.14. Embedded Debug Features 7.15. Timing Closure Recommendations 7.16. Transceiver Register Map 7.17. Loading IP Configuration Settings 7.18. Dynamic Reconfiguration Revision History
7.7. Multiple Reconfiguration Profiles x
7.7.1. Reconfiguration Files 7.7.2. Embedded Reconfiguration Streamer
7.7.2. Embedded Reconfiguration Streamer x
7.7.2.1. Register 0x40140 7.7.2.2. Register 0x40141
7.12. Dynamic Reconfiguration Flow for Special Cases x
7.12.1. Switching Reference Clocks 7.12.2. Reconfiguring PMA Settings
7.12.1. Switching Reference Clocks x
7.12.1.1. Switching Between Any Two refclk[0, 1, 2, 3, 4, 5, 6, 7] Reference Clocks or Changing the Reference Clock Frequency on refclk[0, 2, 3, 4, 5, 6, 7, 8] 7.12.1.2. Switching from/to refclk[0, 1, 2, 3, 4, 5, 6, 7] to/from refclk[8] 7.12.1.3. Changing the refclk[1] Reference Clock Frequency
7.14. Embedded Debug Features x
7.14.1. Native PHY Debug Master Endpoint (NPDME) 7.14.2. Optional Dynamic Reconfiguration Logic
7.14.2. Optional Dynamic Reconfiguration Logic x
7.14.2.1. Capability Registers 7.14.2.2. Control and Status Registers
7.17. Loading IP Configuration Settings x
7.17.1. Loading IP Configuration Settings Process 7.17.2. Alternative Method for Setting PMA Attributes
8. Dynamic Reconfiguration Examples x
8.1. Reconfiguring the Duplex PMA Using the Reset Controller in Automatic Mode 8.2. PRBS Usage Model 8.3. PMA Error Injection 8.4. PMA Receiver Equalization Adaptation Usage Model 8.5. User-Defined Pattern Example 8.6. Configuring the Attenuation Value (VOD) 8.7. Configuring the Post Emphasis Value 8.8. Configuring pretap1 Values 8.9. Inverting TX Polarity for the PMA Driver 8.10. Inverting RX Polarity for the PMA Driver 8.11. Configuring a PMA Parameter Tunable by the Adaptive Engine 8.12. Configuring a PMA Parameter Using Native PHY IP 8.13. Enabling Low Power Mode for Multiple Channels 8.14. Initializing an RX 8.15. Resetting the RX Equalization 8.16. Dynamic Reconfiguration Examples Revision History
8.12. Configuring a PMA Parameter Using Native PHY IP x
8.12.1. PMA Bring Up Flow Using Native PHY IP 8.12.2. Native PHY IP GUI Details 8.12.3. Loading a PMA Configuration
9. Register Map x
9.1. PMA Register Map 9.2. PMA Attribute Codes 9.3. PMA Registers 0x200 to 0x203 Usage 9.4. Supported Data Rate Ratios for PMA Attribute Codes 0x0005 and 0x0006 9.5. RS-FEC Registers 9.6. Register Map Revision History
9.1. PMA Register Map x
9.1.1. PMA Capability Registers 9.1.2. PMA Control and Status Registers 9.1.3. PMA Avalon® Memory-Mapped Interface
9.2. PMA Attribute Codes x
9.2.1. 0x0001: PMA Enable/Disable 9.2.2. 0x0002: PMA PRBS Settings 9.2.3. 0x0003: Data Comparison Set Up and Start/Stop 9.2.4. 0x0005: TX Channel Divide By Ratio 9.2.5. 0x0006: RX Channel Divide By Ratio 9.2.6. 0x0008: Internal Serial Loopback and Reverse Parallel Loopback Control 9.2.7. 0x000A: Receiver Tuning Controls 9.2.8. 0x000E: RX Phase Slip 9.2.9. 0x0011: PMA TX/RX Calibration 9.2.10. 0x0013: TX/RX Polarity and Gray Code Encoding 9.2.11. 0x0014: TX/RX Width Mode 9.2.12. 0x0015: TX Equalization 9.2.13. 0x0017: Error Counter Reset 9.2.14. 0x0018: Status/Debug Register 9.2.15. 0x0019: Status/Debug Register Next Write Field 9.2.16. 0x001A: Status/Debug Register Next Read Field 9.2.17. 0x001B: TX Error Injection Signal 9.2.18. 0x001C: Incoming RX Data Capture 9.2.19. 0x001E: Error Count Status 9.2.20. 0x0020: Electrical Idle Detector 9.2.21. 0x002B: RX Termination and TX Driver Tri-state Behavior 9.2.22. 0x0030: PMA Mux Clock Swap 9.2.23. 0x0126: Read Receiver Tuning Parameters 9.2.24. Reading and Writing PMA Analog Parameters Using Attributes
9.2.24. Reading and Writing PMA Analog Parameters Using Attributes x
9.2.24.1. Reading PMA Analog Parameters 9.2.24.2. Updating PMA Analog Parameters 9.2.24.3. Loading Parameters into the Receiver 9.2.24.4. Fixing Parameter Values 9.2.24.5. Reading NRZ/PAM4 Eye Height 9.2.24.6. Enabling and Disabling Electrical Idle Detector Filtering and Reading Electrical Idle Detector Status 9.2.24.7. Initial Adaptation Effort Levels
9.3. PMA Registers 0x200 to 0x203 Usage x
9.3.1. PMA Analog Reset 9.3.2. Set PRBS Mode and Internal Serial Loopback 9.3.3. Use Cases for Opcode START_ADAPTATION 9.3.4. Read the Physical Channel Number 9.3.5. Check the PMA Adaptation Status 9.3.6. Load a PMA Configuration using Opcode LOAD_PMA_CONFIGURATION
9.5. RS-FEC Registers x
9.5.1. rsfec_top_clk_cfg 9.5.2. rsfec_top_tx_cfg 9.5.3. rsfec_top_rx_cfg 9.5.4. tx_aib_dsk_conf 9.5.5. rsfec_core_cfg 9.5.6. rsfec_lane_cfg 9.5.7. tx_aib_dsk_status 9.5.8. rsfec_debug_cfg 9.5.9. rsfec_lane_tx_stat 9.5.10. rsfec_lane_tx_hold 9.5.11. rsfec_lane_tx_inten 9.5.12. rsfec_lane_rx_stat 9.5.13. rsfec_lane_rx_hold 9.5.14. rsfec_lane_rx_inten 9.5.15. rsfec_lanes_rx_stat 9.5.16. rsfec_lanes_rx_hold 9.5.17. rsfec_lanes_rx_inten 9.5.18. rsfec_ln_mapping_rx 9.5.19. rsfec_ln_skew_rx 9.5.20. rsfec_cw_pos_rx 9.5.21. rsfec_core_ecc_hold 9.5.22. rsfec_err_inj_tx 9.5.23. rsfec_err_val_tx 9.5.24. rsfec_corr_cw_cnt (Low) 9.5.25. rsfec_corr_cw_cnt (High) 9.5.26. rsfec_uncorr_cw_cnt (Low) 9.5.27. rsfec_uncorr_cw_cnt (High) 9.5.28. rsfec_corr_syms_cnt (Low) 9.5.29. rsfec_corr_syms_cnt (High) 9.5.30. rsfec_corr_0s_cnt (Low) 9.5.31. rsfec_corr_0s_cnt (High) 9.5.32. rsfec_corr_1s_cnt (Low) 9.5.33. rsfec_corr_1s_cnt (High)
10. Debugging E-Tile Transceiver Links x
10.1. E-Tile Transceiver Toolkit Overview 10.2. E-Tile Transceiver Debugging Flow Walkthrough 10.3. Modifying the Design to Enable E-Tile Transceiver Debug 10.4. Programming the Design into an Intel FPGA 10.5. Loading the Design in the E-Tile Transceiver Toolkit 10.6. Verifying E-Tile Hardware Connections 10.7. Running Transceiver Tests 10.8. Controlling PMA Analog Settings 10.9. Debugging E-Tile Transceiver Links Revision History
10.3. Modifying the Design to Enable E-Tile Transceiver Debug x
10.3.1. Debug Parameters for the E-Tile Transceiver IP in the Parameter Editor 10.3.2. Debug Parameters for Stratix® 10 E-Tile Transceiver Native PHY IP in the Parameter Editor 10.3.3. Instantiating and Parameterizing E-Tile Transceiver IP
10.7. Running Transceiver Tests x
10.7.1. Running BER Tests 10.7.2. Link Optimization Tests 10.7.3. Running Eye Viewer Tests
A. E-Tile Channel Placement Tool x
A.1. E-Tile Channel Placement Tool Revision History
B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation x
B.1. Building Blocks and Considerations B.2. Starting a New Quartus® Prime Pro Edition Design B.3. Selecting the Configuration Clock Source B.4. Instantiating the Transceiver Native PHY IP B.5. Instantiating the In-system Sources and Probes Intel® FPGA IP B.6. Making the Top Level Connection B.7. Assigning Pins B.8. Bringing up the Board B.9. Debug Tools B.10. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation Revision History
B.9. Debug Tools x
B.9.1. Monitoring Transceiver Signals
C. Signal Detect Algorithm x
C.1. Signal Detect Algorithm Revision History
D. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode x
D.1. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode Revision History
E. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode x
E.1. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode Revision History
F. Hold Timing Violation x
F.1. Hold Timing Violation Revision History
1. E-Tile Transceiver PHY Overview
2. Implementing the Transceiver PHY Layer
3. E-Tile Transceiver PHY Architecture
4. Clock Network
5. PMA Calibration
6. Resetting Transceiver Channels
7. Dynamic Reconfiguration
8. Dynamic Reconfiguration Examples
9. Register Map
10. Debugging E-Tile Transceiver Links
A. E-Tile Channel Placement Tool
B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation
C. Signal Detect Algorithm
D. Detailed Steps for Reconfiguring from Mission Mode to Channel Protection Mode
E. Detailed Steps for Reconfiguring from Channel Protection Mode to Mission Mode
F. Hold Timing Violation

9.5. RS-FEC Registers

The delay between RS-FEC register reads should be at least 10 μs. There is no such requirement for register writes. As a result, RS-FEC register back-to-back writes are allowed.

In order to get reliable readouts of the registers with addresses greater than 0x100, ensure RS-FEC has a valid clock.

Reconfiguration and status monitoring of the RS-FEC block in the E-tile Native PHY IP core is provided through a dedicated Avalon® memory-mapped interface. This interface specifically reads and writes the control and status registers associated with the RS-FEC block. A separate Avalon® memory-mapped interface, called the channel Avalon® memory-mapped interface, reads and writes the control and status registers associated with the other blocks in the E-tile Native PHY IP core.

The Avalon® memory-mapped interface for the RS-FEC consists of eight interface ports exposed at the top level of the Native PHY IP core.

Table 82.  RS-FEC Avalon® Memory-Mapped Interface Ports
Port Name Direction   Clock Domain Width
reconfig_rsfec_clk Input wire N/A  
reconfig_rsfec_reset Input wire reconfig_rsfec_clk  
reconfig_rsfec_write Input wire reconfig_rsfec_clk  
reconfig_rsfec_read Input wire reconfig_rsfec_clk  
reconfig_rsfec_address Input wire reconfig_rsfec_clk [10:0]
reconfig_rsfec_writedata Input wire reconfig_rsfec_clk [7:0]
reconfig_rsfec_readdata Output wire reconfig_rsfec_clk [7:0]
reconfig_rsfec_waitrequest Output wire reconfig_rsfec_clk  

The reconfig_rsfec_clk input must be driven by a 100-125 MHz clock. The same clock can be used for this input as for the channel Avalon® memory-mapped interface.

The reconfig_rsfec_reset input must be asserted for at least one clock cycle of the reconfiguration clock after the device has entered user mode. The Reset IP can be used to provide this reset signal.

The reconfig_rsfec_write and reconfig_rsfec_read inputs are used to indicate to the Avalon® memory-mapped interface whether a read or write operation is desired. The reconfig_rsfec_address input is used for both read and write operations and indicates which register address is targeted during the current Avalon® Memory-Mapped Interface access operation.

The reconfig_rsfec_writedata and reconfig_rsfec_readdata contain the data to be written to or the data read from the register address set by the 11 bit reconfig_rsfec_address input.

The reconfig_rsfec_writedata and reconfig_rsfec_readdata ports are 8 bits wide. The RS-FEC registers, in the hardware, are 32 bits wide, but they use 4 byte increment addressing, so the 32 bit register can be addressed as four 8 bit registers with contiguous byte addresses.

For example, the least-significant byte (lowest order byte) of register 0x04 (where register address 0x04 is considered as a 32 bit register address) is accessed by reading 8 bits from or writing 8 bits to address 0x04. To get the next most significant byte of the same 32 bit register, read 8 bits from or write 8 bits to address 0x05. To get the rest of the register, use addresses 0x06 and 0x07. The next 32 bit register has an address of 0x08. In other words, the 32 bit register addresses increment by 4 bytes for each register.

Effectively, the registers are addressed, read, and written one byte at a time. This matches the hardware implementation of the Avalon® memory-mapped interface.

The reconfig_rsfec_waitrequest output asserts when the Avalon® memory-mapped interface is busy servicing an Avalon® Memory-Mapped Interface operation and deasserts when the Avalon® Memory-Mapped Interface is available for the next operation.

Table 83.  RS-FEC Registers
Address Name Description Reset
0x04 rsfec_top_clk_cfg RS-FEC Clock configuration register 0x0000 0F00
0x10 rsfec_top_tx_cfg RS-FEC TX configuration register 0x0000 0000
0x14 rsfec_top_rx_cfg RS-FEC RX configuration register 0x0000 0000
0x20 tx_aib_dsk_conf Defines the configuration fields for TX Deskew 0x0000 0000
0x30 rsfec_core_cfg RS-FEC core configuration 0x0000 0000
0x40 rsfec_lane_cfg_0 RS-FEC per lane configuration 0x0000 0000
0x44 rsfec_lane_cfg_1
0x48 rsfec_lane_cfg_2
0x4C rsfec_lane_cfg_3
0x104 tx_aib_dsk_status Status fields for TX Deskew 0x0000 0000
0x108 rsfec_debug_cfg Extra config/debug on fec_clock 0x0000 0000
0x120 rsfec_lane_tx_stat_0 RS-FEC per lane TX status 0x0000 0000
0x124 rsfec_lane_tx_stat_1
0x128 rsfec_lane_tx_stat_2
0x12C rsfec_lane_tx_stat_3
0x130 rsfec_lane_tx_hold_0 RS-FEC per lane TX status hold 0x0000 0000
0x134 rsfec_lane_tx_hold_1
0x138 rsfec_lane_tx_hold_2
0x13C rsfec_lane_tx_hold_3
0x140 rsfec_lane_tx_inten_0 RS-FEC per lane TX status hold interrupt - set to 1 to enable rsfec_lane_tx lane interrupt 0x0000 0000
0x144 rsfec_lane_tx_inten_1
0x148 rsfec_lane_tx_inten_2
0x14C rsfec_lane_tx_inten_3
0x150 rsfec_lane_rx_stat_0 RS-FEC per lane RX status 0x0000 0000
0x154 rsfec_lane_rx_stat_1
0x158 rsfec_lane_rx_stat_2
0x15C rsfec_lane_rx_stat_3
0x160 rsfec_lane_rx_hold_0 RS-FEC per lane RX status hold 0x0000 0000
0x164 rsfec_lane_rx_hold_1
0x168 rsfec_lane_rx_hold_2
0x16C rsfec_lane_rx_hold_3
0x170 rsfec_lane_rx_inten_0 RS-FEC per lane RX status hold interrupt - set to 1 to enable rsfec_lane_rx lane interrupt 0x0000 0000
0x174 rsfec_lane_rx_inten_1
0x178 rsfec_lane_rx_inten_2
0x17C rsfec_lane_rx_inten_3
0x180 rsfec_lanes_rx_stat RS-FEC combined lanes RX status 0x0000 0000
0x188 rsfec_lanes_rx_hold RS-FEC combined lanes RX hold status 0x0000 0000
0x18C rsfec_lanes_rx_inten RS-FEC combined lanes RX interrupt enable - set to 1 to enable rsfec_lanes RX lane interrupt 0x0000 0000
0x1A0 rsfec_ln_mapping_rx_0 RS-FEC FEC lane mapping 0x0000 0000
0x1A4 rsfec_ln_mapping_rx_1
0x1A8 rsfec_ln_mapping_rx_2
0x1AC rsfec_ln_mapping_rx_3
0x1B0 rsfec_ln_skew_rx_0 RS-FEC lane skew 0x0000 0000
0x1B4 rsfec_ln_skew_rx_1
0x1B8 rsfec_ln_skew_rx_2
0x1BC rsfec_ln_skew_rx_3
0x1C0 rsfec_cw_pos_rx_0 RS-FEC codeword bit position on RX 0x0000 0000
0x1C4 rsfec_cw_pos_rx_1
0x1C8 rsfec_cw_pos_rx_2
0x1CC rsfec_cw_pos_rx_3
0x1D0 rsfec_core_ecc_hold RS-FEC SRAM ECC status hold 0x0000 0000
0x1E0 rsfec_err_inj_tx_0 RS-FEC error injection mode 0x0000 0000
0x1E4 rsfec_err_inj_tx_1
0x1E8 rsfec_err_inj_tx_2
0x1EC rsfec_err_inj_tx_3
0x1F0 rsfec_err_val_tx_0 RS-FEC per lane error injection status 0x0000 0000
0x1F4 rsfec_err_val_tx_1
0x1F8 rsfec_err_val_tx_2
0x1FC rsfec_err_val_tx_3
0x200 rsfec_corr_cw_cnt_0_lo RS-FEC number of FEC codewords with errors that were corrected (low word: bits 31 to 0) 0x0000 0000
0x208 rsfec_corr_cw_cnt_1_lo
0x210 rsfec_corr_cw_cnt_2_lo
0x218 rsfec_corr_cw_cnt_3_lo
0x204 rsfec_corr_cw_cnt_0_hi RS-FEC number of FEC codewords with errors that were corrected (high word: bits 63 to 32) 0x0000 0000
0x20C rsfec_corr_cw_cnt_1_hi
0x214 rsfec_corr_cw_cnt_2_hi
0x21C rsfec_corr_cw_cnt_3_hi
0x220 rsfec_uncorr_cw_cnt_0_lo RS-FEC number of FEC codewords that could not be corrected due to too many errors (low word: bits 31 to 0) 0x0000 0000
0x228 rsfec_uncorr_cw_cnt_1_lo
0x230 rsfec_uncorr_cw_cnt_2_lo
0x238 rsfec_uncorr_cw_cnt_3_lo
0x224 rsfec_uncorr_cw_cnt_0_hi RS-FEC number of FEC codewords that could not be corrected due to too many errors (high word: bits 63 to 32) 0x0000 0000
0x22C rsfec_uncorr_cw_cnt_1_hi
0x234 rsfec_uncorr_cw_cnt_2_hi
0x23C rsfec_uncorr_cw_cnt_3_hi
0x240 rsfec_corr_syms_cnt_0_lo RS-FEC number of 10b symbols corrected for the lane (low word: bits 31 to 0) 0x0000 0000
0x248 rsfec_corr_syms_cnt_1_lo
0x250 rsfec_corr_syms_cnt_2_lo
0x258 rsfec_corr_syms_cnt_3_lo
0x244 rsfec_corr_syms_cnt_0_hi RS-FEC number of 10b symbols corrected for the lane (high word: bits 63 to 32) 0x0000 0000
0x24C rsfec_corr_syms_cnt_1_hi
0x254 rsfec_corr_syms_cnt_2_hi
0x25C rsfec_corr_syms_cnt_3_hi
0x260 rsfec_corr_0s_cnt_0_lo RS-FEC number of bits corrected 0->1 for the lane (low word: bits 31 to 0) 0x0000 0000
0x268 rsfec_corr_0s_cnt_1_lo
0x270 rsfec_corr_0s_cnt_2_lo
0x278 rsfec_corr_0s_cnt_3_lo
0x264 rsfec_corr_0s_cnt_0_hi RS-FEC number of bits corrected 0->1 for the lane (high word: bits 63 to 32) 0x0000 0000
0x26C rsfec_corr_0s_cnt_1_hi
0x274 rsfec_corr_0s_cnt_2_hi
0x27C rsfec_corr_0s_cnt_3_hi
0x280 rsfec_corr_1s_cnt_0_lo RS-FEC number of bits corrected 1->0 for the lane (low word: bits 31 to 0) 0x0000 0000
0x288 rsfec_corr_1s_cnt_1_lo
0x290 rsfec_corr_1s_cnt_2_lo
0x298 rsfec_corr_1s_cnt_3_lo
0x284 rsfec_corr_1s_cnt_0_hi RS-FEC number of bits corrected 1->0 for the lane (high word: bits 63 to 32) 0x0000 0000
0x28C rsfec_corr_1s_cnt_1_hi
0x294 rsfec_corr_1s_cnt_2_hi
0x29C rsfec_corr_1s_cnt_3_hi

All statistic registers are 64 bits, and you must do two 32-bit reads. Intel recommends that you enable the shadow_req[3:0] in offset address 0x108 explained in rsfec_debug_cfg before reading the statistics register and disable after reading it.


Section Content
rsfec_top_clk_cfg
rsfec_top_tx_cfg
rsfec_top_rx_cfg
tx_aib_dsk_conf
rsfec_core_cfg
rsfec_lane_cfg
tx_aib_dsk_status
rsfec_debug_cfg
rsfec_lane_tx_stat
rsfec_lane_tx_hold
rsfec_lane_tx_inten
rsfec_lane_rx_stat
rsfec_lane_rx_hold
rsfec_lane_rx_inten
rsfec_lanes_rx_stat
rsfec_lanes_rx_hold
rsfec_lanes_rx_inten
rsfec_ln_mapping_rx
rsfec_ln_skew_rx
rsfec_cw_pos_rx
rsfec_core_ecc_hold
rsfec_err_inj_tx
rsfec_err_val_tx
rsfec_corr_cw_cnt (Low)
rsfec_corr_cw_cnt (High)
rsfec_uncorr_cw_cnt (Low)
rsfec_uncorr_cw_cnt (High)
rsfec_corr_syms_cnt (Low)
rsfec_corr_syms_cnt (High)
rsfec_corr_0s_cnt (Low)
rsfec_corr_0s_cnt (High)
rsfec_corr_1s_cnt (Low)
rsfec_corr_1s_cnt (High)

Related Information
Level Two Title