E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 8/08/2023
Public

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4.5.8. Steps to Disable FEC

The following steps provide a procedure for disabling FEC for the 100G variant as handled in the C-code generated in the IP folder (dynamic_reconfig.cpp). This procedure is executed based on the values configured through the dynamic reconfiguration registers as per the software routines in the Design Example.

RS-FEC configuration to disable RS-FEC:

  • [R1] Bypass FEC - Write 0x0000 to RS-FEC register 0x14 ([rsfec_top_rx_cfg]
  • [R2] Disable FEC clock - Write 0x0000 to RS-FEC register 0x04 ([rsfec_top_clk_cfg]

Transceiver configuration:

  • [T1] Write 0xCB to Transceiver channel register 0x4[7:0]
  • [T2] Write 0x4C to Transceiver channel register 0x5[7:0]
  • [T3] Write 0x0F to Transceiver channel register 0x6[7:0]
  • [T4] Write 0xA6 to Transceiver channel register 0x7[7:0]
  • [T5] Write 0xA5 to Transceiver channel register 0xA4[7:0]
  • [T6] Write 0xA5 to Transceiver channel register 0xA8[7:0]
  • [T7] Write 0x55 to Transceiver channel register 0xB0[7:0]
  • [T8] Write 0x07 to Transceiver channel register 0xE8[7:0]
Note: Repeat steps 2a to 2h for each Transceiver channel.

Ethernet configuration:

  • [E1] Write 0x312C7 to Ethernet register 0x37A
  • [E2] Write 0x9FFD8028 to Ethernet register 0x40B
  • [E3] Set bits [3] and [9] of Ethernet register 0x30E (Use RX PCS Alignment)