Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

6.3.8. Uncorrectable Internal Error Status Register

This register reports the status of the internally checked errors that are uncorrectable. When specific errors are enabled by the Uncorrectable Internal Error Mask register, they are handled as Uncorrectable Internal Errors as defined in the PCI Express Base Specification 3.0. This register is for debug only. Use this register to observe behavior, not to drive custom logic.

Table 34.  Uncorrectable Internal Error Status Register (Byte Offset: 0x234)
Bits Reset Value Access Description
[31:12] 0x00 RO Reserved.
[11] 1'b0 RW1CS A value of 1 indicates an RX buffer overflow condition in a posted request or Completion segment.
[10] 1'b0 RW1CS A value of 1 indicates a parity error was detected on the R2CSEB interface.
[9] 1'b0 RW1CS A value of 1 indicates a parity error was detected on the Configuration Space to TX bus interface.
[8] 1'b0 RW1CS A value of 1 indicates a parity error was detected on the TX to Configuration Space bus interface.
[7] 1'b0 RW1CS A value of 1 indicates a parity error was detected in a TX TLP and the TLP is not sent.
[6] 1'b0 RW1CS A value of 1 indicates that the Application Layer has detected an uncorrectable internal error.
[5] 1'b0 RW1CS A value of 1 indicates a configuration error has been detected in CvP mode which is reported as uncorrectable. This CVP_CONFIG_ERROR_LATCHED bit is set whenever a CVP_CONFIG_ERROR is asserted while in CVP_MODE.
[4] 1'b0 RW1CS A value of 1 indicates a parity error was detected by the TX Data Link Layer.
[3] 1'b0 RW1CS A value of 1 indicates a parity error has been detected on the RX to Configuration Space bus interface.
[2] 1'b0 RW1CS A value of 1 indicates a parity error was detected at input to the RX Buffer.
[1] 1'b0 RW1CS A value of 1 indicates a retry buffer uncorrectable ECC error.
[0] 1'b0 RW1CS A value of 1 indicates a RX buffer uncorrectable ECC error.