Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

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ID 721605
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform Board Restore
3.3. Perform Board Restore x
3.3.1. Restore Board System Intel® MAX® 10 with Default Factory Image 3.3.2. Restore Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCA NRZ Tab 4.2.5.4. The FMCB NRZ Tab 4.2.5.5. The QSFPDD800 PAM4 Tab 4.2.5.6. The MXPM NRZ Tab 4.2.5.7. The MXPM PAM4 Tab 4.2.5.8. The SDI Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the AS Mode (Default Mode) 5.3. Configure the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.3. Clocks

Table 9.  Default Clock Frequency
Schematic Signal Name Default Frequency
DDR4_HPS_REFCLKp/n 166.6M
DDR4_DIMM_2_REFCLKp/n 166.6M
Si5332_OUT2_P/N 100M
Si5332_OUT3_P/N 100M
PCIE_100M_REF_RP_AP/N 100M
Si5332_OUT5_P/N 100M
CLK_GPIO_P_4/N_4 100M
Si5332_OUT7_P/N 100M
Si5391_A_OUT_P0A/N0A 156.25M
Si5391_A_OUT_P0/N0 156.25M
Si5391_A_OUT_P1/N1 156.25M
Si5391_A_OUT_P5/N5 184.32M
Si5391_A_OUT_P6/N6 148.5M
Si5391_A_OUT_P7/N7 368.63M
Si5391_A_OUT_P9/N9 153.6M
Si5391_B_OUT_P0/N0 156.25M
CLK_13A_FGT_REFCLK4_P/N 156.25M
CLK_13A_FGT_REFCLK2_P/N 184.32M
Si5391_B_OUT_P5/N 184.32M
Si5391_B_OUT_P6/N6 148.5M
Si5391_B_OUT_P7/N7 368.63M
Si5391_B_OUT_P9/N9 153.6M
CLK_13A_FGT_REFCLK3_P/N 153.6M
CLK_FHT_13A_P_0/N_0 156.25M
CLK_FHT_13C_P_0/N_0 156.25M
CLK_FGT_13C_REFCLK_2P/N 135M
CLK_A_12C_FGT_P_0/N_0 100M
CLK_3A_GPIO_P_0/N_0 100M
CLK_A_12C_FGT_P_3/N_3 148.5M
CLK_3A_GPIO_P_2/N_2 148.5M
CLK_A_12C_FGT_P_2/N_2 156.25M
CLK_3A_GPIO_P_1/N_1 156.25M
CLK_A_12C_FGT_P_4/N_4 156.25M
CLK_A_12C_FGT_P_6/N_6 368.63M
CLK_A_12C_FGT_P_5/N_5 184.32M
CLK_B_12A_FGT_P_0/N_0 100M
CLK_13A_FGT_REFCLK0_P/N 100M
CLK_B_12A_FGT_P_2/N_2 156.25M
CLK_3C_GPIO_P_1/N_1 156.25M
CLK_B_12A_FGT_P_3/N_3 148.5M
CLK_3C_GPIO_P_0/N_0 148.5M
CLK_B_12A_FGT_P_4 156.25M
CLK_B_12A_FGT_P_5 184.32M
CLK_B_12A_FGT_P_6 368.63M
ToD_CLK_100M_P/N 100M
ETH_REFCLK_156.25M_P/N 156.25M
CPRI_REFCLK_153.6M_P/N 153.6M
CPRI_REFCLK_184.32M_P/N 184.32M
FMCA_REFCLK_148.5M_P/N 148.5M
FMCA_REFCLK_156.25M_P/N 156.25M
Si5391_A_156.25M_REFIN_P/N 156.25M
Si5391_B_156.25M_REFIN_P/N 156.25M
CLK_3C_GPIO_P_1/N_1 156.25M
CLK_B_12A_FGT_P_3/N_3 148.5M
CLK_3C_GPIO_P_0/N_0 148.5M
1PPS_FPGA_CLK 1PPS
1PPS_SMA_OUT 1PPS
10MHz_SMA_OUT 10M
ZL_SPARE_CLK_100M 100M
Figure 35. Clock Tree
Level Two Title