Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

Download PDF
ID 721605
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform Board Restore
3.3. Perform Board Restore x
3.3.1. Restore Board System Intel® MAX® 10 with Default Factory Image 3.3.2. Restore Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCA NRZ Tab 4.2.5.4. The FMCB NRZ Tab 4.2.5.5. The QSFPDD800 PAM4 Tab 4.2.5.6. The MXPM NRZ Tab 4.2.5.7. The MXPM PAM4 Tab 4.2.5.8. The SDI Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the AS Mode (Default Mode) 5.3. Configure the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

3.1. Default Settings

The Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the factory default switch settings table to return to its factory settings before proceeding ahead.

Note: X refers to Don't Care in the table below.
Note: Don't set the switches when the power is on. Only set the switches after the power is off.
Table 4.  Factory Default Switch Settings
Switch Default Position Default Function
S19 [1:4] OFF/OFF/ON/ON System Intel® MAX® 10 and FPGA selected in JTAG chain.
S20 [1:4] ON/ON/ON/ON

Mode 1: On-board Intel® download circuit act as the only JTAG master.

Chained HPS with SDM nodes internally.
S9 [1:4] ON/OFF/OFF/X

Configuration mode setting bits:

AS - Fast mode
S10 [1:4] ON/ON/ON/ON

SYS_SW[0:3]

  • SYS_SW[0]—Factory Loadn
  • ‘0’—Load image from Page 0 of the QSPI
  • SYS_SW[1]—MUX_SEL1
  • SYS_SW[2]—MUX_SEL7
  • SYS_SW[3]—MUX_SEL9
S15 [1:4] ON/ON/ON/OFF

SYS_SW[4:7]

  • SYS_SW[4]—MUX_SEL_ZL
  • SYS_SW[5]—FMC-A PCIe RP/EP Select
    • “0”: RP (Default)
    • “1”: EP
  • SYS_SW[6]—FMC-B PCIe RP/EP Select
    • “0”: RP (Default)
    • “1”: EP
  • SYS_SW[7]—MCIO PCIe RP/EP Select
    • “0”: RP
    • “1”: EP (Default)
S1 [1:4] OFF/OFF/OFF/OFF User Switch [0:3]
S6 [1:4] OFF/OFF/OFF/OFF User Switch [4:7]
S22 [1:4] ON/ON/ON/ON

MUX_DIP_SW[0:3]

  • MUX_DIP_SW0—MUX_SEL2
  • MUX_DIP_SW1—MUX_SEL3
  • MUX_DIP_SW2—MUX_SEL4
  • MUX_DIP_SW3—MUX_SEL5

Set to "ON" by default to select on-board clock as input.
S23 [1:4] ON/ ON / ON / ON

MUX_DIP_SW[4:7]

  • MUX_DIP_SW4—MUX_SEL10
  • MUX_DIP_SW5—MUX_SEL11
  • MUX_DIP_SW6—MUX_SEL12
  • MUX_DIP_SW7—MUX_SEL14

Set “0”/closed by default for on-board clock as input.
S4 [1:4] ON/ ON / ON / ON

MUX_DIP_SW[8:11]

  • MUX_DIP_SW8—MUX_SEL13
  • MUX_DIP_SW9—MUX_SEL6
  • MUX_DIP_SW10—MUX_SEL0
  • MUX_DIP_SW11—MUX_SEL8

Set “0”/closed by default for on-board clock as input.
Level Two Title