Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

Download PDF
ID 721605
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform Board Restore
3.3. Perform Board Restore x
3.3.1. Restore Board System Intel® MAX® 10 with Default Factory Image 3.3.2. Restore Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCA NRZ Tab 4.2.5.4. The FMCB NRZ Tab 4.2.5.5. The QSFPDD800 PAM4 Tab 4.2.5.6. The MXPM NRZ Tab 4.2.5.7. The MXPM PAM4 Tab 4.2.5.8. The SDI Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the AS Mode (Default Mode) 5.3. Configure the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

1.2. Feature Summary

  • Intel Agilex® 7 FPGA I-Series, 2.7M LE, 3184B package
  • F-Tile 1 (13C)
    • 4 FHT transceiver channels fan out to Quad Small Form Factor Double Density 800 (QSFPDD800)
    • 8 FGT transceiver channels to Quad Small Form Factor Double Density connector
    • 2 FGT transceiver channels to HD-BNC for SDI
    • 4 FGT transceiver as DP2.0 1
    • 1FGT transceiver for USB3.21
  • F-Tile 2 (13A)
    • 4 FHT transceiver channels (116G) to MXPM
    • 8 FGT transceiver channels (56G) to MXPM
    • 8 FGT transceiver channels to Quad Small Form Factor Double Density connector
    • 4 FGT transceiver channels to MCIO ( PCIe* )
  • F-Tile 3 (12C)
    • 16 FGT channels to FMC+
  • F-Tile 4 (12A)
    • 16 FGT channels to FMC+
  • SR DDR4 2666 (x72 w/ ECC), 16GB
  • 8GB SR DDR4-2666 (x72 w/ ECC) component down (HPS)
  • IO48 interface for HPS Out of Box Experience (OOBE) daughter cards
1 Preliminary
Level Two Title