Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

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ID 721605
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform Board Restore
3.3. Perform Board Restore x
3.3.1. Restore Board System Intel® MAX® 10 with Default Factory Image 3.3.2. Restore Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCA NRZ Tab 4.2.5.4. The FMCB NRZ Tab 4.2.5.5. The QSFPDD800 PAM4 Tab 4.2.5.6. The MXPM NRZ Tab 4.2.5.7. The MXPM PAM4 Tab 4.2.5.8. The SDI Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the AS Mode (Default Mode) 5.3. Configure the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.4. General Input/Output

Table 10.   Intel® MAX® 10 and FPGA
Schematic Signal Name Description
F_GPIO0 The value of filtered user_pb[0]
F_GPIO1 The value of filtered user_pb[1]
F_GPIO2 MCIO_PERST in RP mode
F_GPIO3 FMC_A_PERST in RP mode
F_GPIO4 FMC_B_PERST in RP mode
F_GPIO5 Status of SYS_SW3 from Intel® MAX® 10
F_GPIO6 Reserved
F_GPIO7 Reserved
F_GPIO8 Reserved
F_GPIO9 Reserved
F_GPIO10 Reserved
F_GPIO11 Reserved
F_GPIO12 Reserved
Table 11.  System Intel® MAX® 10
Schematic Signal Name Description
SYS_LED0/D9 PGM_LED0 for Avalon® -ST configuration
SYS_LED1/D11 PGM_LED1 for Avalon® -ST configuration
SYS_LED2/D13 PGM_LED2 for Avalon® -ST configuration
SYS_LED3/D15 MAX_ERROR for Avalon® -ST configuration
SYS_LED4/D10 MAX_LOAD for Avalon® -ST configuration
SYS_LED5/D12 MAX_CONF_DONE for Avalon® -ST configuration
SYS_LED6/D14 Reserved
SYS_LED7/D16 Reserved
SYS_PB0/S11 MAX_RESETn
SYS_PB1/S12 FPGA_RESETn
SYS_PB2/S13 HPS_COLD_RESETn
SYS_PB3/S14 Power recycle
SYS_PB4/S16 PGM_SEL for Avalon® -ST configuration
SYS_PB5/S17 PGM_CFG for Avalon® -ST configuration
clk_i2c_en0

Before power ok: 0

After power ok: S_control_gui[2], =1 by default

clk_i2c_en1 Stuck at GND
VCCL_I2C_EN

Before power ok: 0

After power ok: S_control_gui[1], =1 by default

dimm_io_en

Before power ok: 0

After power ok: 1
zl_i2c_en

Before power ok: 0

After power ok: S_control_gui[3], =0 by default

si5394_rstn

When input globe resetn active: 0

When input globe resetn release: S_control_gui[13], =1 by default

si5394_oe_n

Before power ok: 1

After power ok: S_control_gui[14], =0 by default

si5391_rstn

When input globe resetn active: 0

When input globe resetn release: S_control_gui[9], =1 by default

si5394_lol Store in status_gui bit3
si5394_int_n Store in status_gui bit2
si5391_oen

Before power ok: 1

After power ok: S_control_gui[10], =0 by default

si5391_b_rstn

When input globe resetn active: 0

When input globe resetn release: S_control_gui[11], =1 by default

si5391_b_oen

Before power ok: 1

After power ok: S_control_gui[12], =0 by default

usb2_resetn

Before power ok: 0

After power ok: S_control_gui[15], =1 by default

usb_mux_reset

Before power ok: 1

After power ok: S_control_gui[16], =0 by default

mux_sel0

system_info_slv_data_write_0[0]=1 : controlled by system_info_slv_data_write_1[0]

system_info_slv_data_write_0[0]=0 : controlled by MUX_DIP_SW10

mux_sel1

system_info_slv_data_write_0[1]=1 : controlled by system_info_slv_data_write_1[1]

system_info_slv_data_write_0[1]=0 : controlled by SYS_SW1

mux_sel2

system_info_slv_data_write_0[2]=1 : controlled by system_info_slv_data_write_1[2]

system_info_slv_data_write_0[2]=0 : controlled by MUX_DIP_SW0

mux_sel3

system_info_slv_data_write_0[3]=1 : controlled by system_info_slv_data_write_1[3]

system_info_slv_data_write_0[3]=0 : controlled by MUX_DIP_SW1

mux_sel4

system_info_slv_data_write_0[4]=1 : controlled by system_info_slv_data_write_1[4]

system_info_slv_data_write_0[4]=0 : controlled by MUX_DIP_SW2

mux_sel5

system_info_slv_data_write_0[5]=1 : controlled by system_info_slv_data_write_1[5]

system_info_slv_data_write_0[5]=0 : controlled by MUX_DIP_SW3

mux_sel6

system_info_slv_data_write_0[6]=1 : controlled by system_info_slv_data_write_1[6]

system_info_slv_data_write_0[6]=0 : controlled by MUX_DIP_SW9

mux_sel7

system_info_slv_data_write_0[7]=1 : controlled by system_info_slv_data_write_1[7]

system_info_slv_data_write_0[7]=0 : controlled by SYS_SW2

mux_sel8

system_info_slv_data_write_0[8]=1 : controlled by system_info_slv_data_write_1[8]

system_info_slv_data_write_0[8]=0 : controlled by MUX_DIP_SW11

mux_sel9

system_info_slv_data_write_0[9]=1 : controlled by system_info_slv_data_write_1[9]

system_info_slv_data_write_0[9]=0 : controlled by SYS_SW3

mux_sel10

system_info_slv_data_write_0[10]=1 : controlled by system_info_slv_data_write_1[10]

system_info_slv_data_write_0[10]=0 : controlled by MUX_DIP_SW4

mux_sel11

system_info_slv_data_write_0[11]=1 : controlled by system_info_slv_data_write_1[11]

system_info_slv_data_write_0[11]=0 : controlled by MUX_DIP_SW5

mux_sel12

system_info_slv_data_write_0[12]=1 : controlled by system_info_slv_data_write_1[12]

system_info_slv_data_write_0[12]=0 : controlled by MUX_DIP_SW6

mux_sel13

system_info_slv_data_write_0[13]=1 : controlled by system_info_slv_data_write_1[13]

system_info_slv_data_write_0[13]=0 : controlled by MUX_DIP_SW8

mux_sel14

system_info_slv_data_write_0[14]=1 : controlled by system_info_slv_data_write_1[14]

system_info_slv_data_write_0[14]=0 : controlled by MUX_DIP_SW7

mux_sel_zl

system_info_slv_data_write_0[15]=1 : controlled by system_info_slv_data_write_1[15]

system_info_slv_data_write_0[15]=0 : controlled by SYS_SW4

mcio_clk_enn

Before power ok: 1

After power ok: S_control_gui[7], =0 by default

mcio_clk_sel_epn

system_info_slv_data_write_0[16]=1 : controlled by S_control_gui[8], =0 by default

system_info_slv_data_write_0[16]=0 :

  • =0 when AGIB027R31B is Endpoint
  • =1 when AGIB027R31B is Root port
si5332_1_in[1:0] S_control_gui[5:4], =00 by default
si5332_1_in[2] 1'bZ
PTP_CLK_RST_n

Before power ok: 0

After power ok: S_control_gui[6], =1 by default

PTP_CLK_LOL Store in status_gui bit1
gpio0_ac0_zl_intn Store in status_gui bit0
Table 12.  UB2/PWR Intel® MAX® 10
Schematic Signal Name Description
FPGA_POK_LED FPGA Power Good
SYS_PWR_RSV0 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10. Used as I2C clock.
SYS_PWR_RSV1 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10. Used as I2C data.
SYS_PWR_RSV2 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10. It is the status of SYS_PB3.
SYS_PWR_RSV3 Reserved GPIO between System Intel® MAX® 10 and Power Intel® MAX® 10
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