External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Public
Document Table of Contents

13.4.3. Calibration

The time needed for calibration varies, depending on many factors including the interface width, the number of ranks, frequency, board layout, and difficulty of calibration.

The following table lists approximate typical calibration times for various protocols and configurations.

Table 396.   Arria® 10 EMIF IP Approximate Calibration Times
Protocol Rank and Frequency Typical Calibration Time
DDR3, x64 UDIMM, DQS x8, DM on 1 rank, 933 MHz 102 ms
1 rank, 800 MHz 106 ms
2 rank, 933 MHz 198 ms
2 rank, 800 MHz 206 ms
DDR4, x64 UDIMM, DQS x8, DBI on 1 rank, 1067 MHz 314 ms
1 rank, 800 MHz 353 ms
2 rank 1067 MHz 625 ms
2 rank 800 MHz 727 ms
RLDRAM 3, x36 1200 MHz 2808 ms
1067 MHz 2825 ms
1200 MHz, with DM 2818 ms
1067 MHz, with DM 2833 ms
QDR II, x36, BWS on 333 MHz 616 ms
633 MHz 833 ms
QDR-IV, x36, BWS on 1067 MHz 1563 ms
1067 MHz, with DBI 1556 ms