External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Public
Document Table of Contents

4.1.3.20. clks_sharing_master_out for LPDDR3

Core clocks sharing master interface

Table 96.  Interface: clks_sharing_master_outInterface type: Conduit
Port Name Direction Description
clks_sharing_master_out Output This port should fanout to all the core clocks sharing slaves.