External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Public
Document Table of Contents

4.1.1.1. pll_ref_clk for DDR3

PLL reference clock input

Table 9.  Interface: pll_ref_clkInterface type: Clock Input
Port Name Direction Description
pll_ref_clk Input PLL reference clock input