E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 3/06/2022
Public

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2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example

The simulation block diagram below is generated using the following settings in the IP parameter editor:
  1. Under the IP tab:
    1. 100GE or 1 to 4 channel 10GE/25GE with optional RSFEC and PTP as the core variant.
    2. 100GE Channel as Active channel(s) at startup.
    3. Enable IEEE 1588 PTP.
    4. Enable RSFEC to use the RS-FEC feature.
  2. Under the 100GE tab:
    1. 100G as the Ethernet rate.
    2. MAC+1588PTP+PCS+(528,514)RSFEC as the Ethernet IP layer.
Figure 14. Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Design Example

In this design example, the testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core.

To speed up simulation, the IP core simulation model sends alignment marker tags at shorter intervals than required by the IEEE Ethernet standard. The standard specifies an alignment marker interval of 16,384 words in each virtual lane. The simulation model with the testbench implements an alignment marker interval of 512 words.

The successful test run displays output confirming the following behavior:

  1. Waiting for PLL to lock.
  2. Waiting for RX transceiver reset to complete.
  3. Waiting for RX alignment.
  4. Sending 10 packets.
  5. Receiving those packets.
  6. Displaying Testbench complete.

The following sample output illustrates a successful simulation test run for a 100GE, MAC+PCS, RS-FEC, PTP IP core variation.

Waiting for RX alignment
RX deskew locked
RX lane aligmnent locked
Configure TX extra latency
====> writedata = 0004267a 

Configure RX extra latency
====> writedata = 8003af52 

Waiting for TX PTP Ready
TX PTP ready
Waiting for RSFEC alignment locked
Reading rsfec_ln_mapping_rx_0
rsfec_ln_mapping_rx_0 = 32'h0
Reading rsfec_ln_skew_rx_0
rsfec_ln_skew_rx_0 = 32'h0
Reading rsfec_cw_pos_rx_0
rsfec_cw_pos_rx_0 = 32'h1c5
.
.
.
Reading rsfec_ln_skew_rx_3
rsfec_ln_skew_rx_3 = 32'h1
Reading rsfec_cw_pos_rx_3
rsfec_cw_pos_rx_3 = 32'h1c5
min skew value = 32'h0
lane_skew_adjust = 32'h0
Tlat_final = 32'h0
Generate VL offset data
before-rotation: VL[PL] 0[0], deskew_delay = 0 UI, vl_offset_bits = 0
After rotation: VL_OFFSET for RVL[PL] 4[0] = 0 ns 0 Fns, Sign bit= 0 
.
.
.
before-rotation: VL[PL] 19[0], deskew_delay = 0 UI, vl_offset_bits = 4
before-rotation: VL[PL] 19[0], deskew_delay = 0 UI, vl_offset_bits_shifted = -326
After rotation: VL_OFFSET for RVL[PL] 3[0] = c ns a515 Fns, Sign bit= 1 
Writing VL offset data for VL 0
====> writedata = 00000004 

====> writedata = 00000000 
.
.
.
Writing VL offset data for VL 19
====> writedata = 00000003 

====> writedata = 800ca515 

Waiting for RX PTP Ready
RX PTP ready
** Sending Packet           1...
** Sending Packet           2...
** Sending Packet           3...
** Sending Packet           4...
** Sending Packet           5...
** Sending Packet           6...
** Sending Packet           7...
** Sending Packet           8...
** Sending Packet           9...
** Received Packet          1...
** Sending Packet          10...
** Received Packet          2...
** Received Packet          3...
** Received Packet          4...
** Received Packet          5...
** Received Packet          6...
** Received Packet          7...
** Received Packet          8...
** Received Packet          9...
** Received Packet         10...
RX and TX timestamp range of difference is from -2.875549 ns to -2.870483 ns
**
** Testbench complete.
**
*****************************************
$finish called from file "basic_avl_tb_top.sv", line 713.
$finish at simulation time           5323700000