E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 3/06/2022
Public

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Document Table of Contents

4.6. Document Revision History for the E-tile Dynamic Reconfiguration Design Example

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.03.06 21.3 20.3.0 Updated directory paths in the following sections:
  • Running the Simulation with Default HEX File
  • Running the Simulation with New HEX File
2021.11.22 21.3 20.3.0
  • Added support for Questa* simulator.
  • Removed support for NCSim simulator.
  • Added new sections:
    • Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
    • Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
    • Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
    • Steps to Enable FEC
    • Steps to Disable FEC
2021.08.11 21.2 20.3.0 Added support for the following in 25G Ethernet to CPRI Dynamic Reconfiguration Design Example:
  • Tunneling mode for CPRI protocol.
  • Dynamic reconfiguration transition to 1G Ethernet.
2021.04.28 20.4 20.3.0 Added a Table: CPRI PHY Soft Configuration Register Space in section: 10GE/25GE Design Examples Registers.
2020.12.14 20.4 20.3.0
  • Added 1GE with PTP variant support for for 25GE with RS-FEC and PTP base operation and 1GE variant support for 25GE with RS-FEC in the 10G/25G Ethernet Dynamic Reconfiguration Design Examples section.
  • Updated following figures in Clocking Scheme section:
    • Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC and PTP Dynamic Reconfiguration Design Example
    • Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC Dynamic Reconfiguration Design Example
  • Updated following diagrams in Simulation Design Examples section:
    • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 10GE/25GE with RS-FEC and PTP Dynamic Reconfiguration Design Example
    • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 10GE/25GE with RS-FEC Dynamic Reconfiguration Design Example
  • Made following changes in sections 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components and 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components:
    • Added description for new blocks.
    • Updated sample output test results.
  • Updated Table: E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Examples Register Map with Triple-Speed Ethernet registers.
  • Added following tables in 10GE/25GE Design Examples Registers section:
    • Table: 1GE Packet Generator Registers
    • Table: 1GE Traffic Monitor Registers
2020.06.29 20.2 20.2.0
  • Added support for dynamic reconfiguration (DR) transitions from high speed CPRI protocol to low PMA-D modes in 25G Ethernet to CPRI Dynamic Reconfiguration Design Example:
    • 24G CPRI with RS-FEC to 10G CPRI
    • 10G CPRI to 9.8G CPRI
    • 9.8G CPRI to 4.9G CPRI
    • 4.9G CPRI to 2.4G CPRI
    • 2.4G CPRI to 24G CPRI with RS-FEC

    Updated DR simulation test sequence and DR hardware test GUI display with the added transitions.

  • Added dl_reset signal in the CPRI PHY Soft Registers table. The reset acts as a soft reset to the deterministic latency block.
2020.04.13 20.1 20.1.0
  • Added support for deterministic latency feature in the 25G Ethernet to CPRI protocol.
    • Updated the Clocking Scheme for 24G CPRI with RS-FEC Dynamic Reconfiguration Design Example figure.
    • Updated the Simulation Block Diagram for 25G Ethernet to CPRI Dynamic Reconfiguration Design Example figure.
    • Updated components described in the 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components section.
    • Added CPRI PHY soft registers table in the 25G Ethernet to CPRI Design Examples Registers section.
  • Updated Clock Control frequency setting in the Testing the E-tile Dynamic Reconfiguration Hardware Design Example section. This setting applies to CPRI and Ethernet to CPRI protocols.
  • Updated TEST_MODE selection in the 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components section. TEST_MODE options are 0, 1, and 2.
2019.12.23 19.4 19.4.0
  • Added simulation, compilation, and timing support for Intel® Stratix® 10 dynamic reconfiguration design examples:
    • 9.8G CPRI with direct PMA
    • 100G Ethernet
  • Restructured topics to improve the content flow.
2019.09.30 19.3 19.3.0
  • Added List of Supported Dynamic Reconfiguration Design Example variants table.
  • Added a note to clarify run_vcs.sh and run_vcsmx.sh usage in the Steps to Simulate the Testbench table.
  • Updated Running the Design Example in Hardware section:
    • Added the board control configuration step
    • Added screenshot of a successful hardware test
  • Updated Power Management Setting for Intel® Stratix® 10 E-tile TX Transceiver Signal Integrity Development Kit section.
  • Added Note: i_channel_PLL is E-tile Transceiver PHY specific signal that utilizes additional transceiver E-tile channel. in the Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC Dynamic Reconfiguration Design Example figure.
  • Updated test run sequence in the 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components section.
  • Replaced clk_100 with clk100 in clocking scheme figures:
    • Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC and PTP Dynamic Reconfiguration Design Example
    • Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC Dynamic Reconfiguration Design Example
    • Clocking Scheme for CPRI with RS-FEC Dynamic Reconfiguration Design Example
  • Added the Calibration Flow for the Hardware Test Script section for all dynamic reconfiguration variants.
  • Added screenshot of the Dynamic Reconfiguration Hardware test for all dynamic reconfiguration variants.
  • Updated Dynamic Reconfiguration Design Example Components sections to include the following steps in the DR tests. Updates are applicable to all DR variants.
    • Disabling SERDES.
    • Triggering PMA analog reset.
    • Adjusting the phase offset of a recovered clock.
    • Enabling SERDES.
19.2.0
  • Added variants: 24G CPRI, 9.8G CPRI, 4.9G CPRI, and 2.4G CPRI in CPRI Dynamic Reconfiguration Design example.
  • Added 25G Ethernet to CPRI Dynamic Reconfiguration simulation, compilation-only project, and hardware design examples.
  • Updated directory structure in E-tile Dynamic Reconfiguration 10G/25G Ethernet and 25G Ethernet to CPRI Design Example Directory Structure and E-tile Dynamic Reconfiguration CPRI With and Without RS-FEC Design Example Directory Structure figures:
    • Added flow.c in software/dynamic_reconfiguration_hardware.
    • Added c3_function.c file in software/dynamic_reconfiguration_hardware and software/dynamic_reconfiguration_sim.
    • Renamed c3_config.c file with c3_recconfig.c in software/dynamic_reconfiguration_hardware and software/dynamic_reconfiguration_sim.
    • Renamed c3_config.h file with c3_recconfig.h file in software/dynamic_reconfiguration_hardware and software/dynamic_reconfiguration_sim.
    • Added cadence and xcelium folders in example_testbench.
    • Renamed eth_25g_pma_direct folder with eth_25g_channel_pll in hardware_test_design.
    • Added reset_release folder in hardware_test_design.
    • Added reset_release.ip file in the hardware_test_design.
  • Added c3_function.c and flow.c functions to dynamic_reconfiguration_sim and dynamic_reconfiguration_hardware directories.
  • Added Ethernet to CPRI Protocol in the E-tile Dynamic Reconfiguration Design Example: Generating the Design section.
  • Added Xcelium* and NCSim simulators support.
  • Renamed 10G/24G CPRI with CPRI globally.
  • Added cpu_resetn and updated i_clk_ref signal's description in the 10GE/25GE Design Example Interface Signals section.
  • Added test cases in the CPRI Protocol reconfiguration flow section.
    • 24G CPRI with RS-FEC to 24G CPRI without RS-FEC
    • 24G CPRI without RS-FEC to 10G CPRI
    • 10G CPRI to 24G CPRI without RS-FEC
    • 24G CPRI without RS-FEC to 24G CPRI with RS-FEC
    • 10G CPRI to 9.8G CPRI
    • 9.8G CPRI to 4.9G CPRI
    • 4.9G CPRI to 2.4G CPRI
  • Updated phy_ref_clk to phy_ref_clk[1:0] signal in the Simulation Block Diagram for CPRI PHY with RS-FEC Dynamic Reconfiguration Design Example figure.
  • Updated bit size to i_clk_ref_cpri[1:0] in the CPRI Hardware Dynamic Reconfiguration Design Example Interface Signals table.
2019.05.17 19.1 19.1 Initial release.