Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC)
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

F-Tile Receiver Specifications

Table 60.  F-Tile FHT Receiver Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Min Typical Max Unit
Receiver input eye specifications VRX-DIFF-PKPK Receiver input differential peak-to-peak voltage Closed eye — 1,200 mVdiff-pkpk
VRX-CM-DC Receiver input DC common-mode voltage97 100 — 900 mV
VRX-MAX Receiver input maximum voltage — — 1,200 mV
VRX-MIN Receiver input minimum voltage –200 — — mV
TRX-DDJ Receive input signal data dependent jitter (inter-symbol interference) — — 1 UIpkpk
TRX-RJ Receive input random jitter — — 0.15 UIpkpk
TRX-PJ Receive input periodic jitter (at high frequency) — — 0.05 UIpkpk
TRX-TJ Receive input total jitter (DDJ + RJ + PJ) — — 1  UIpkpk
Equalizer specifications FPPM-OFFSET Tolerable data frequency offset –200 — 200 ppm
Receiver return loss ZRL-DIFF-DC Receiver differential DC return loss — — 10 dB
ZRL-DIFF-NYQ Receiver differential return loss at Nyquist frequency (FBAUD/2) — — 6 dB
ZRL-CM Receiver common-mode return loss below 10 GHz — — 6 dB
Receiver DC impedance RDIFF-DC DC differential receive impedance 80 100 120 Ω
RCM-DC DC common-mode receive impedance 20 25 30 Ω
Table 61.  F-Tile FGT Receiver Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Min Typical Max Unit
Receiver input eye specifications VRX-DIFF-PKPK Receiver input differential peak-to-peak voltage98 Closed eye — 1,200 mV
VRX-MAX Receiver input maximum voltage99 — — 1 V
VRX-MIN Receiver input minimum voltage99 –0.3 — — V
VRX-CM-DC Receiver input DC common-mode voltage100 0 — 700 mV
TRX-RJ Receive input random jitter — — 0.15 UIpkpk
TRX-PJ Receive input periodic jitter (at high frequency) — — 0.05 UIpkpk
Insertion loss specifications IINS-LOSS-56Gb/s Insertion loss at 56 Gbps PAM42/BER <10–4 — — 30 dB
IINS-LOSS-53Gb/s Insertion loss at 53 Gbps PAM42/BER <10–4 5101 — — dB
IINS-LOSS-30Gb/s Insertion loss at 32 Gbps NRZ102 /BER <10–12 — — 30 dB
IINS-LOSS-25Gb/s Insertion loss at 25.78125 Gbps NRZ102/ BER <10–12 — — 30 dB
Receiver return loss ZRL-DIFF-DC Receiver differential DC return loss — — 12 dB
ZRL-DIFF-NYQ Receiver differential return loss at Nyquist frequency (FBAUD/2) — — 6 dB
ZRL-CM Receiver common-mode return loss below 10 GHz — — 6 dB
Receiver DC impedance RDIFF-DC DC differential receive impedance 65 85 102 Ω
80 100 120 Ω
RCM-DC DC common-mode receive impedance 20 25 30 Ω
Receiver signal detection103 VIDLE-THRESH Receiver signal detect input voltage threshold 75 120 175 mVdiff-pkpk
97 Referenced to RX GND. This specification is also supported before mode configuration.
98 This is supported when the receiver is powered and configured, powered and unconfigured, or unpowered.
99 VRX_MAX and VRX_MIN are before and after configuration.
100 The specified common-mode range is supported when the receiver is powered and configured, powered and unconfigured, or unpowered. This specification is also supported before mode configuration. If squelch detect is used, receiver DC input common-mode voltage should be within 200 mV to 300 mV. Otherwise, use AC coupling capacitors on board.
101 The minimum insertion loss specification assumes a PAM4 transmitter with 800 mVppd. For transmitters with output amplitude adjustment capabilities and can reduce output amplitude to below 800 mVppd, this minimum insertion loss can be further relaxed.
102 COM compliant package and channel.
103 Receiver signal detection values in this table are applicable to PCIe* and similar standards, such as SATA, where a clock pattern like PCIe* EIEOS 500 MHz clock pattern is used.
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