Visible to Intel only — GUID: fkf1657772365416
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: fkf1657772365416
Ixiasoft
JTAG Configuration Timing
Symbol | Description | Requirement | Unit | |
---|---|---|---|---|
Minimum | Maximum | |||
tJCP | TCK clock period | 30 | — | ns |
tJCH | TCK clock high time | 14 | — | ns |
tJCL | TCK clock low time | 14 | — | ns |
tJPSU (TDI) 129 | TDI JTAG port setup time | 2 | — | ns |
tJPSU (TMS) 129 | TMS JTAG port setup time | 3 | — | ns |
tJPH 129 | JTAG port hold time | 5 | — | ns |
tJPCO | JTAG port clock to output | — | 7130 | ns |
tJPZX | JTAG port high impedance to valid output | — | 14 | ns |
tJPXZ | JTAG port valid output to high impedance | — | 14 | ns |
Figure 27. JTAG Timing Diagram
129 For boundary-scan testing, the TMS and TDI JTAG ports minimum setup time and hold time are 7 ns.
130 Capacitance loading at 10 pF.