Visible to Intel only — GUID: hxv1657772121618
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: hxv1657772121618
Ixiasoft
GPIO-B Differential POD I/O Standards Specifications
I/O Standard | VCCIO_PIO (V) | VILdiff(DC) (V) | VIHdiff(DC) (V) | VILdiff(AC) (V) | VIHdiff(AC) (V) | VIX(AC) (%)43 | ||
---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Max | Min | Max | Min | Max | |
POD1244 | 1.164 | 1.2 | 1.236 | –0.11 | 0.11 | –0.14 | 0.14 | 25 |
POD1144 | 1.067 | 1.1 | 1.133 | –0.11 | 0.11 | –0.14 | 0.14 | 25 |
43 Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.
44 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire GPIO-B sub-bank is operating in any of the following modes:
- LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
- PHYLITE mode
- GPIO mode