Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC)
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

HPS Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 73.  Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) TX_CLK clock period — 8 — ns
Tclk (100Base-T) TX_CLK clock period — 40 — ns
Tclk (10Base-T) TX_CLK clock period — 400 — ns
Tdutycycle (1000Base-T) TX_CLK duty cycle 45 50 55 %
Tdutycycle (10/100Base-T) TX_CLK duty cycle 40 50 60 %
Td 112 113 TXD/TX_CTL to TX_CLK output skew –0.5 — 0.5 ns
Figure 11. RGMII TX Timing Diagram
Table 74.  RGMII RX Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) RX_CLK clock period — 8 — ns
Tclk (100Base-T) RX_CLK clock period — 40 — ns
Tclk (10Base-T) RX_CLK clock period — 400 — ns
Tdutycycle (1000Base-T) RX_CLK duty cycle 45 50 55 %
Tdutycycle (10/100Base-T) RX_CLK duty cycle 40 50 60 %
Tsu RX_D/RX_CTL to RX_CLK setup time 1 — — ns
Th 114 RX_CLK to RX_D/RX_CTL hold time 1 — — ns
Figure 12. RGMII RX Timing Diagram
Table 75.  Reduced Media Independent Interface (RMII) Clock Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tclk REF_CLK clock period, sourced by HPS TX_CLK — 20 — ns
REF_CLK clock period, sourced by external clock source — 20 — ns
Tdutycycle_int Clock duty cycle, REF_CLK sourced by TX_CLK 35 50 65 %
Tdutycycle_ext Clock duty cycle, REF_CLK sourced by external clock source 35 50 65 %
Table 76.  RMII TX Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Td TX_CLK to TXD/TX_CTL output data delay 2 — 10 ns
Figure 13. RMII TX Timing Diagram
Table 77.  RMII RX Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tsu RX_D/RX_CTL setup time 2 — — ns
Th RX_D/RX_CTL hold time 1 — — ns
Figure 14. RMII RX Timing Diagram
Table 78.  Management Data Input/Output (MDIO) Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tclk MDC clock period 400 — — ns
Td MDC to MDIO output data delay 10 — 300 ns
Tsu Setup time for MDIO data 10 — — ns
Th Hold time for MDIO data 0 — — ns
Figure 15. MDIO Timing Diagram
Related Information
112 Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
113 If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5—2.0 ns with the HPS I/O programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement.
114 If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5 – 2 ns, using the HPS I/O programmable delay.
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