Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC)
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

Recommended Operating Conditions

Table 9.  Recommended Operating Conditions

This table lists the steady-state voltage values expected. Power supply ramps must all be strictly monotonic, without plateaus.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum13 Typical Maximum13 Unit
VCC Core voltage power supply SmartVID14 : –1V, –2V, –3V, –3E (Typical) – 3% 0.70 – 0.9015 (Typical) + 3% V
VCCP Periphery circuitry power supply SmartVID14: –1V, –2V, –3V, –3E (Typical) – 3% 0.70 – 0.9015 (Typical) + 3% V
VCCPT Power supply for I/O PLL and I/O pre-driver — 1.71 1.8 1.89 V
VCCRCORE CRAM power supply — 1.14 1.2 1.26 V
VCCH Advanced interface bus (AIB) power supply Devices with R-Tile and F-Tile 0.776 0.8 0.824 V
Devices with F-Tile only 0.776 0.8 0.824 V
VCCH_SDM SDM block transceiver digital power sense Devices with R-Tile and F-Tile 0.87 0.9 0.93 V
Devices with F-Tile only 0.776 0.8 0.824 V
VCCIO_UIB Power supply for the Universal Interface Bus between the core and embedded HBM2E memory — 1.17 1.2 1.23 V
VCCIO_PIO_SDM 16 SDM block I/O bank power sense of Bank 3A 1.05 V17 1.0185 1.05 1.0815 V
1.1 V17 1.067 1.1 1.133 V
1.2 V17 1.164 1.2 1.236 V
1.3 V 1.261 1.3 1.339 V
VCCIO_SDM SDM block configuration pins power supply — 1.71 1.8 1.89 V
VCCL_SDM SDM block core voltage power supply — 0.776 0.8 0.824 V
VCCFUSEWR_SDM SDM block fuse writing power supply — 1.75 1.8 1.85 V
VCCPLLDIG_SDM SDM block PLL digital power supply — 0.776 0.8 0.824 V
VCCPLL_SDM SDM block PLL analog power supply — 1.71 1.8 1.89 V
VCCM_PUMP_HBM HBM2E power supply — 2.4 2.5 2.6 V
VCCBAT 18 Battery back-up power supply (For design security volatile key register) — 1 — 1.8 V
IBAT Battery back-up power supply (For design security volatile key register) VCCBAT = 1.2 V — — 200 nA
VCCADC ADC voltage sensor power supply — 1.71 1.8 1.89 V
VCCIO_PIO I/O bank power supply 1.05 V17 1.0185 1.05 1.0815 V
1.1 V17 1.067 1.1 1.133 V
1.2 V17 1.164 1.2 1.236 V
1.3 V 1.261 1.3 1.339 V
VCCIO_NOC NOC configuration pins power supply — 1.71 1.8 1.89 V
VCCPLL_NOC NOC PLL analog power supply — 1.71 1.8 1.89 V
VCCPLLDIG_NOC NOC PLL digital power supply — 0.776 0.8 0.824 V
VCCLPLL_NOC NOC PLL core voltage power supply — 0.776 0.8 0.824 V
VI 19 DC input voltage VCCIO_PIO = 1.05 V20 21 –0.3 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.1 V20 21 –0.3 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.2 V20 21 –0.3 — VCCIO_PIO + 0.25 V
VCCIO_PIO = 1.3 V20 21 –0.3 — VCCIO_PIO + 0.25 V
VCCIO_SDM = 1.8 V –0.3 — VCCIO_SDM + 0.3 V
VCCIO_HPS = 1.8 V –0.3 — VCCIO_HPS + 0.3 V
VO Output voltage VCCIO_PIO = 1.05 V, 1.1 V, 1.2 V, 1.3 V 0 — VCCIO_PIO V
VCCIO_SDM = 1.8 V 0 — VCCIO_SDM V
VCCIO_HPS = 1.8 V 0 — VCCIO_HPS V
TJ Operating junction temperature Extended 022 — 10023 24 °C
IFUSEWR_SDM SDM fuse Current Static — — 50 mA
Dynamic average AC during sensing and programming — 0.6 — mA
tRAMP 25 26 Power supply ramp time Standard POR 200 μs — 100 ms —
13 This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise.
14 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
15 The typical value is based on the SmartVID programmed value.
16 Must be powered up with the same voltage level as VCCIO_PIO_3A or tie to VCCRCORE when VCCIO_PIO for 3A bank is not in configuration. Must be supplied at 1.2 V when using Avalon® Streaming ×16/×32 configuration schemes.
17 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire GPIO-B sub-bank is operating in any of the following modes:
  • LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
  • PHYLITE mode
  • GPIO mode
18 Power up VCCBAT with a non-volatile battery power source when using the device security AES BBRAM key. When not using the AES BBRAM key, tie this pin to ground.
19 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
20 Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
21 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI (DC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V.
22 Intel Agilex® 7 M-Series devices are generally offered in Extended temperature range only. If an industrial temperature range is required, note that you can configure these devices at less than 0°C, but the HBM2 interface will be held reset and not calibrated until Tj reaches 0°C. Contact your Intel sales representative for the availability of Intel Agilex® 7 M-Series Industrial temperature range devices.
23 When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device lifetime of 11.4 years.
24 The recommended maximum operating temperature for HBM2E devices is 95°C.
25 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
26 To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating conditions.
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