AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

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ID 683072
Date 7/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices 3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example 8. Achieving Timing Closure on a Motor Control Design 9. Design Security Recommendations 10. Reference Documents for the Drive-on-Chip Design Example 11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.1. Software Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up the Motor Control Board with your Development Board for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.5. Importing the Drive-On-Chip Design Example Software Project 3.6. Configuring the FPGA Hardware for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.7. Programming the Nios II Software to the Device for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.8. Applying Power to the Power Board 3.9. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 3.10. System Console GUI Upper Pane for the Drive-On-Chip Design Example 3.11. System Console GUI Lower Pane for the Drive-On-Chip Design Example 3.12. Controlling the DC-DC Converter 3.13. Tuning the PI Controller Gains 3.14. Controlling the Speed and Position Demonstrations 3.15. Monitoring Performance
3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.2.1. Preparing the Rechargeable Battery
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
4.1. Changing the Intel® MAX® 10 ADC Thresholds or Conversion Sequence 4.2. Generating the Qsys System 4.3. Compiling the Hardware in the Intel Quartus Prime Software 4.4. Generating and Building the Nios II BSP for the Drive-On-Chip Design Example 4.5. Software Application Configuration Files 4.6. Compiling the Software Application for the Drive-On-Chip Design Example 4.7. Programming the Design into Flash Memory
4.5. Software Application Configuration Files x
4.5.1. Defining a New Motor or Encoder Type
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta and MAX 10 Integrated ADCs 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the System Console Toolkit
6. Motor Control Software x
6.1. Viewing Motor Control Software Help Files
7. Functional Description of the Drive-on-Chip Design Example x
7.1. Processor Subsystem 7.2. Six-channel PWM Interface 7.3. DC Link Monitor 7.4. Drive System Monitor 7.5. Quadrature Encoder Interface 7.6. Sigma-Delta ADC Interface for Drive Axes 7.7. Intel® MAX® 10 ADCs 7.8. ADC Threshold Sink 7.9. DC-DC Converter 7.10. Motor Control Modes 7.11. FOC Subsystem 7.12. DEKF Technique 7.13. Signals 7.14. Registers
7.4. Drive System Monitor x
7.4.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.6. Sigma-Delta ADC Interface for Drive Axes x
7.6.1. Offset Adjustment for Sigma-Delta ADC Interface
7.9. DC-DC Converter x
Low-Voltage Two-phase DC-DC Boost Converter 7.9.1. DC-DC Control Simulink Models 7.9.2. Sigma-Delta ADC Interface for DC-DC Converter
7.9.1. DC-DC Control Simulink Models x
7.9.1.1. DC-DC Control Block 7.9.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
7.9.1.1. DC-DC Control Block x
7.9.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
7.11. FOC Subsystem x
7.11.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.11.2. Avalon Memory-Mapped Interface 7.11.3. About DSP Builder for Intel FPGAs 7.11.4. DSP Builder for Intel FPGAs Folding 7.11.5. DSP Builder for Intel FPGAs Model Resource Usage 7.11.6. DSP Builder for Intel FPGAs Design Guidelines 7.11.7. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
8. Achieving Timing Closure on a Motor Control Design x
8.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example
8. Achieving Timing Closure on a Motor Control Design
9. Design Security Recommendations
10. Reference Documents for the Drive-on-Chip Design Example
11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices

7.9. DC-DC Converter

The Drive-On-Chip Design Example DC-DC converter comprises two-phase DC-DC converter power electronics on the Tandem Motion-Power 48 V board and IP.
Figure 30. DC-DC Converter Block Diagram

The power electronics hardware includes:

  • Two inductors (phases)
  • Two MOSFET half-bridges
  • MOSFET gate driver chip per MOSFET half-bridge
  • Current sensing of each inductor current: the total DC link input current and the total DC link output current
  • Voltage sensing of the DC Link input voltage and DC Link output voltage

The low voltage two-phase DC-DC boost converter includes:

  • Three sigma-delta ADC interfaces
  • DC-DC control block
  • Avalon memory-mapped agent interface for control and status
  • Fault flag logic

Intel developed the converter using DSP Builder for Intel FPGAs.

The DC-DC converter consists of 2 phases that provide bidirectional power flow from a low voltage power source or battery (typically 12 V DC) to a DC link output bus (maximum 48 V DC) that feeds one or more motor drive inverters. The DC-DC converter provides the boost function to increase the voltage. It also provides a buck function during periods of regenerative braking to deliver power from the DC link output bus back to the low voltage source (i.e., battery in this case).

The gate driving signals for the two phases are 180 degrees out of phase so that they alternate in supplying current during buck-boost function, which gives smoother output current and voltage.

The control consists of two independent inner current loops and an outer voltage loop that regulates the DC link output bus voltage to a specified value (e.g., 32 V DC). An external host (e.g. the Nios II processor) gives the target value via the Avalon memory mapped agent interface.

For feedback control, the DC-DC control block takes the output of the two inductor current and DC link output voltage ADCs outputs. The design connects the outputs of the DC link input voltage, the DC link input current, and the DC link output current ADCs with DC link monitors to detect fault conditions for external host monitoring.

Low-Voltage Two-phase DC-DC Boost Converter

The top-level module of the DC-DC converter is a Qsys component, which is a manually-created HDL module that:

  • Instantiates the VHDL entity generated by DSP Builder for Intel FPGAs (the DC-DC control block)
  • Instantiates sigma-delta ADC interface module
  • Adds an Avalon memory-mapped register agent and conduit signals.

The design instantiates the DC-DC Converter in the lvmc_dclink.qsys subsystem.

You can instantiate the Qsys component in a Qsys system and connect it to the Nios II processor and other modules. The register agent allows software access to the DC-DC converter parameters, control, and status. The conduits connect to various system-wide control and status signals that are outside the software domain.

The top-level module implements safety features in the fault flag logic that you may use with external logic, to protect the system in the case of a malfunction. The fault flag logic combines (logical ORs) three fault bit signals provided by the DC link monitors. They monitor the total DC link input current, the DC link input voltage, and the total DC link output current, and gate the following two independent enable sources that enable the DC-DC converter:

  • The enable bit in the control register
  • The enable input for the DSP Builder block.

The ADC interface in the DC-DC converter has three demodulators for one-bit sigma-delta signals, which sense the following DC link feedback signals:

  • The output voltage
  • The two output inductor currents

The ADC interface delivers 16-bit ADC values at 156 kHz, which is 1/128 of 20 MHz. The design feeds the ADC output values to the DC-DC control block to carry out the feedback control loops. The voltage feedback control and two inductor current feedback control loops run autonomously in hardware, without software interaction in the loop execution.


Section Content
DC-DC Control Simulink Models
Sigma-Delta ADC Interface for DC-DC Converter

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