AN 773: Drive-On-Chip Design Example for Intel® MAX® 10 Devices

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ID 683072
Date 7/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices 3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 5. About the Scaling of Feedback Signals 6. Motor Control Software 7. Functional Description of the Drive-on-Chip Design Example 8. Achieving Timing Closure on a Motor Control Design 9. Design Security Recommendations 10. Reference Documents for the Drive-on-Chip Design Example 11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.1. Software Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.3. Downloading and Installing the Design 3.4. Setting Up the Motor Control Board with your Development Board for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.5. Importing the Drive-On-Chip Design Example Software Project 3.6. Configuring the FPGA Hardware for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.7. Programming the Nios II Software to the Device for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices 3.8. Applying Power to the Power Board 3.9. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 3.10. System Console GUI Upper Pane for the Drive-On-Chip Design Example 3.11. System Console GUI Lower Pane for the Drive-On-Chip Design Example 3.12. Controlling the DC-DC Converter 3.13. Tuning the PI Controller Gains 3.14. Controlling the Speed and Position Demonstrations 3.15. Monitoring Performance
3.2. Hardware Requirements for the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
3.2.1. Preparing the Rechargeable Battery
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices x
4.1. Changing the Intel® MAX® 10 ADC Thresholds or Conversion Sequence 4.2. Generating the Qsys System 4.3. Compiling the Hardware in the Intel Quartus Prime Software 4.4. Generating and Building the Nios II BSP for the Drive-On-Chip Design Example 4.5. Software Application Configuration Files 4.6. Compiling the Software Application for the Drive-On-Chip Design Example 4.7. Programming the Design into Flash Memory
4.5. Software Application Configuration Files x
4.5.1. Defining a New Motor or Encoder Type
5. About the Scaling of Feedback Signals x
5.1. Signal Sensing in Sigma-Delta and MAX 10 Integrated ADCs 5.2. Signal Scaling in the Software of the Drive-on-Chip Design Example 5.3. Scale Factors for the Drive-on-Chip Design Example in the System Console Toolkit
6. Motor Control Software x
6.1. Viewing Motor Control Software Help Files
7. Functional Description of the Drive-on-Chip Design Example x
7.1. Processor Subsystem 7.2. Six-channel PWM Interface 7.3. DC Link Monitor 7.4. Drive System Monitor 7.5. Quadrature Encoder Interface 7.6. Sigma-Delta ADC Interface for Drive Axes 7.7. Intel® MAX® 10 ADCs 7.8. ADC Threshold Sink 7.9. DC-DC Converter 7.10. Motor Control Modes 7.11. FOC Subsystem 7.12. DEKF Technique 7.13. Signals 7.14. Registers
7.4. Drive System Monitor x
7.4.1. Drive System Monitor States for the Drive-on-Chip Design Example
7.6. Sigma-Delta ADC Interface for Drive Axes x
7.6.1. Offset Adjustment for Sigma-Delta ADC Interface
7.9. DC-DC Converter x
7.9.1. DC-DC Control Simulink Models 7.9.2. Sigma-Delta ADC Interface for DC-DC Converter
7.9.1. DC-DC Control Simulink Models x
7.9.1.1. DC-DC Control Block 7.9.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
7.9.1.1. DC-DC Control Block x
7.9.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
7.11. FOC Subsystem x
7.11.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs 7.11.2. Avalon Memory-Mapped Interface 7.11.3. About DSP Builder for Intel FPGAs 7.11.4. DSP Builder for Intel FPGAs Folding 7.11.5. DSP Builder for Intel FPGAs Model Resource Usage 7.11.6. DSP Builder for Intel FPGAs Design Guidelines 7.11.7. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
8. Achieving Timing Closure on a Motor Control Design x
8.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
2. Features of the Drive-on-Chip Design Example for Intel® MAX® 10 Devices
3. Getting Started with the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
4. Rebuilding the Drive-On-Chip Design Example for Intel® MAX® 10 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example
8. Achieving Timing Closure on a Motor Control Design
9. Design Security Recommendations
10. Reference Documents for the Drive-on-Chip Design Example
11. Document Revision History for AN 773: Drive-on-Chip Design Example for Intel® MAX® 10 Devices

4.7. Programming the Design into Flash Memory

For the Drive-On-Chip Design Example for Intel® MAX® 10 devices, you can store the FPGA configuration file in the Intel® MAX® 10 on-chip flash memory; you can store the software executable in external QSPI flash memory.
  1. Rebuild the design with the Nios II reset vector pointing to the QSPI memory
    The quartus.ini file with PGMIO_SWAP_HEX_BYTE_DATA=ON content is required in the project directory.
  2. Compile the software and generate the software programmer object file.
    1. In the Nios II SBT, open the BSP editor.
    2. Unselect all advanced.hal.linker option.
    3. Modify the linker script to point the reset section to the qspi memory.
    4. Build the BSP project and the main project.
    5. Generate the .hex file by right-clicking DOC_TANDEM_MAX10 > Make Targets > Build > mem_init_generate.
    6. In the Quartus Prime software click File > Convert Programming Files and enter these settings:.
      • Configuration device: CFI_512Mb.
      • Mode: 1-bit Passive Serial.
    7. Change the file name to the desired path and name. For example SW.pof.
    8. In Input files to convert, remove SOF Page_0.
    9. Click ADD HEX Data,
    10. Choose the generic_quad_spi_controller_0.hex file generated previously in step 2e.
      This file is in the mem_init subdirectory of the software project.
    11. Select Absolute Addressing and click OK.
    12. Click Generate to create the .pof file.
  3. Program the software into QSPI flash.
    1. Ensure DIP SW2 is set to OFF-ON-ON-ON.
    2. Download the parallel Flash Loader from rocket boards https://rocketboards.org/foswiki/pub/Documentation/AlteraMAX1010M50RevCDevelopmentKitLinuxSetup/max10_qpfl.sof.
    3. Program the parallel flash loader (max10_qpfl.sof) into the MAX 10 device to program the QSPI flash, using Quartus Programmer.
    4. Right click on the MAX 10 FPGA and select Edit > Change File.
    5. Choose the max_qpfl.sof file.
    6. Turn on MAX 10 device under Program/Configure.
    7. Click Start to start programming.
    8. Click on Auto Detect after max10_qpfl.sof was successful.
      A new QSPI flash device is shown, attached to the MAX10.
    9. Program the software image into QSPI flash.
    10. Right click on the SQPI device and select Edit > Change File
    11. Choose the generated .pof file (SW.pof).
    12. Check the .hex file under Program/Configure.
    13. Click Start to start programming.
  4. Program hardware .sof file into the MAX 10 FPGA.
    1. Right click on the MAX 10 FPGA and select Edit > Change File.
    2. Choose the .sof file generated from Quartus Prime project compilation.
    3. Click Start to start programming.
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