Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

8.3.2.5. Address Remapping

The system interconnect supports address remapping through the remap register in the l3regs group. Remapping allows software to control which memory device (SDRAM, on-chip RAM, or boot ROM) is accessible at address 0x0 and the accessibility of the HPS-to-FPGA and lightweight HPS-to-FPGA bridges. The remap register is one of the NIC-301 Global Programmers View (GPV) registers. The following L3 masters can manipulate remap, because it maps into their address space:

  • MPU
  • FPGA-to-HPS bridge
  • DAP

The remapping bits in the remap register are not mutually exclusive. The lowest order remap bit has higher priority when multiple slaves are remapped to the same address. Each bit allows different combinations of address maps to be formed. There is only one remapping register available in the GPV, so modifying the remap register affects all memory maps of all the masters of the system interconnect.

The effects of the remap bits can be categorized in the following groups:

  • MPU master interface
    • L2 cache master 0 interface
  • Non-MPU master interfaces
    • DMA master interface
    • Master peripheral interfaces
    • Debug Access Port (DAP) master interface
    • FPGA-to-HPS bridge master interface
Note: L2 filter registers in the MPU subsystem, not the interconnect, allow the SDRAM to be remapped to address 0x0 for the MPU.